EDJ4216EFBG-L Datasheet PDF - Micron

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EDJ4216EFBG-L
Micron

Part Number EDJ4216EFBG-L
Description 32 Meg x 16 x 8 banks DDR3L-RS SDRAM
Page 30 Pages


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4Gb: x8, x16 DDR3L-RS SDRAM
Description
DDR3L-RS SDRAM
EDJ4208EFBG-L – 64 Meg x 8 x 8 banks
EDJ4216EFBG-L – 32 Meg x 16 x 8 banks
Description
The 1.35V DDR3L-RS SDRAM device is a low-voltage
version of the DDR3 (1.5V) SDRAM. Refer to the DDR3
(1.5V) SDRAM data sheet specifications when running
in 1.5V-compatible mode.
Features
• VDD = VDDQ = 1.35V (1.283–1.45V)
• Backward compatible to VDD = VDDQ = 1.5V ±0.075V
– Supports DDR3L devices to be backward com-
patible in 1.5V applications
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• Programmable partial-array self refresh (PASR)
• Reduced self refresh current
– IDD6: 2.2mA (TYP) at 25ºC
• TC of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Options
• Configuration
– 512 Meg x 8
– 256 Meg x 16
• FBGA package (Pb-free) – x8
– 78-ball (9mm x 10.6mm) Rev. F
• FBGA package (Pb-free) – x16
– 96-ball FBGA (9mm x 13.5mm) Rev. F
• Timing – cycle time
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
• Operating temperature
– Commercial (0°C TC +95°C)1
• Revision: F
Note: 1. No guarantee on industrial and automotive
temperature ranges.
Table 1: Key Timing Parameters
Speed Grade
-GN2
-DJ1
Data Rate (MT/s)
1600
1333
Target tRCD-tRP-CL
11-11-11
9-9-9
Notes: 1. Backward compatible to 1066, CL = 7.
2. Backward compatible to 1333, CL = 9.
Table 2: Addressing
Parameter
Configuration
Refresh count
512 Meg x 8
64 Meg x 8 x 8 banks
8K
tRCD (ns)
13.75
13.5
tRP (ns)
13.75
13.5
CL (ns)
13.75
13.5
256 Meg x 16
32 Meg x 16 x 8 banks
8K
PDF: 09005aef859bddc0
4Gb_DDR3L_RS_F_EDJ.pdf - Rev. A 4/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.



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Table 2: Addressing (Continued)
Parameter
Row address
Bank address
Column address
Page size
512 Meg x 8
64K (A[15:0])
8 (BA[2:0])
1K (A[9:0])
1KB
4Gb: x8, x16 DDR3L-RS SDRAM
Description
256 Meg x 16
32K (A[14:0])
8 (BA[2:0])
1K (A[9:0])
2KB
Figure 1: DDR3L-RS Part Numbers
E D J 42 04 E F BG - GN L - F - D
Micron Technology
(Micron Japan)
Type
D = Packaged device
Product Family
J = DDR3 SDRAM
Density/Bank
42 = 4Gb/8-bank
Organization
04 = x4
08 = x8
16 = x16
Packing Media
D = Dry Pack (Tray)
R = Tape and Reel
Environment Code
F = Lead-free (RoHS-compliant)
and halogen-free
Special Detail
L = Reduced self refresh
Speed
GN = DDR3L-1600 (11-11-11)
DJ = DDR3L-1333 (9-9-9)
Package
BG = FBGA
Revision
Power Supply
E = 1.35V
Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
PDF: 09005aef859bddc0
4Gb_DDR3L_RS_F_EDJ.pdf - Rev. A 4/14 EN
2 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.



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4Gb: x8, x16 DDR3L-RS SDRAM
Description
Contents
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
Industrial Temperature ............................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 22
Electrical Specifications .................................................................................................................................. 24
Absolute Ratings ......................................................................................................................................... 24
Input/Output Capacitance .......................................................................................................................... 25
Thermal Characteristics .................................................................................................................................. 26
Electrical Specifications – IDD Specifications and Conditions ............................................................................ 27
Electrical Characteristics – DDR3L (1.35V) Operating IDD Specifications ........................................................... 38
Electrical Specifications – DC and AC .............................................................................................................. 39
DC Operating Conditions ........................................................................................................................... 39
Input Operating Conditions ........................................................................................................................ 40
DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 44
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 47
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 49
ODT Characteristics ....................................................................................................................................... 50
1.35V ODT Resistors ................................................................................................................................... 51
ODT Sensitivity .......................................................................................................................................... 52
ODT Timing Definitions ............................................................................................................................. 52
Output Driver Impedance ............................................................................................................................... 56
34 Ohm Output Driver Impedance .............................................................................................................. 57
DDR3L 34 Ohm Driver ................................................................................................................................ 58
DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 59
DDR3L Alternative 40 Ohm Driver ............................................................................................................... 60
DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 60
Output Characteristics and Operating Conditions ............................................................................................ 62
Reference Output Load ............................................................................................................................... 65
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 65
Slew Rate Definitions for Differential Output Signals .................................................................................... 67
Speed Bin Tables ............................................................................................................................................ 68
Electrical Characteristics and AC Operating Conditions ................................................................................... 70
Command and Address Setup, Hold, and Derating ........................................................................................... 89
Data Setup, Hold, and Derating ....................................................................................................................... 96
Commands – Truth Tables ............................................................................................................................. 104
Commands ................................................................................................................................................... 107
DESELECT ................................................................................................................................................ 107
NO OPERATION ........................................................................................................................................ 107
ZQ CALIBRATION LONG ........................................................................................................................... 107
ZQ CALIBRATION SHORT .......................................................................................................................... 107
ACTIVATE ................................................................................................................................................. 107
READ ........................................................................................................................................................ 107
WRITE ...................................................................................................................................................... 108
PRECHARGE ............................................................................................................................................. 109
REFRESH .................................................................................................................................................. 109
SELF REFRESH .......................................................................................................................................... 110
DLL Disable Mode ..................................................................................................................................... 111
PDF: 09005aef859bddc0
4Gb_DDR3L_RS_F_EDJ.pdf - Rev. A 4/14 EN
3 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.



No Preview Available !

4Gb: x8, x16 DDR3L-RS SDRAM
Description
Input Clock Frequency Change ...................................................................................................................... 115
Write Leveling ............................................................................................................................................... 117
Write Leveling Procedure ........................................................................................................................... 119
Write Leveling Mode Exit Procedure ........................................................................................................... 121
Initialization ................................................................................................................................................. 122
Voltage Initialization / Change ....................................................................................................................... 124
VDD Voltage Switching ............................................................................................................................... 125
Mode Registers .............................................................................................................................................. 126
Mode Register 0 (MR0) ................................................................................................................................... 127
Burst Length ............................................................................................................................................. 127
Burst Type ................................................................................................................................................. 128
DLL RESET ................................................................................................................................................ 129
Write Recovery .......................................................................................................................................... 129
Precharge Power-Down (Precharge PD) ...................................................................................................... 130
CAS Latency (CL) ....................................................................................................................................... 130
Mode Register 1 (MR1) ................................................................................................................................... 131
DLL Enable/DLL Disable ........................................................................................................................... 131
Output Drive Strength ............................................................................................................................... 132
OUTPUT ENABLE/DISABLE ...................................................................................................................... 132
TDQS Enable ............................................................................................................................................. 132
On-Die Termination .................................................................................................................................. 133
WRITE LEVELING ..................................................................................................................................... 133
POSTED CAS ADDITIVE Latency ................................................................................................................ 133
Mode Register 2 (MR2) ................................................................................................................................... 134
CAS Write Latency (CWL) ........................................................................................................................... 135
AUTO SELF REFRESH (ASR) ....................................................................................................................... 135
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 136
SRT vs. ASR ............................................................................................................................................... 136
DYNAMIC ODT ......................................................................................................................................... 136
Mode Register 3 (MR3) ................................................................................................................................... 137
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 137
MPR Functional Description ...................................................................................................................... 138
MPR Register Address Definitions and Bursting Order ................................................................................. 139
MPR Read Predefined Pattern .................................................................................................................... 144
MODE REGISTER SET (MRS) Command ........................................................................................................ 144
ZQ CALIBRATION Operation ......................................................................................................................... 145
ACTIVATE Operation ..................................................................................................................................... 146
READ Operation ............................................................................................................................................ 148
WRITE Operation .......................................................................................................................................... 159
DQ Input Timing ....................................................................................................................................... 167
PRECHARGE Operation ................................................................................................................................. 169
SELF REFRESH Operation .............................................................................................................................. 169
Extended Temperature Usage ........................................................................................................................ 171
Power-Down Mode ........................................................................................................................................ 172
RESET Operation ........................................................................................................................................... 180
On-Die Termination (ODT) ............................................................................................................................ 182
Functional Representation of ODT ............................................................................................................. 182
Nominal ODT ............................................................................................................................................ 182
Dynamic ODT ............................................................................................................................................... 184
Dynamic ODT Special Use Case ................................................................................................................. 184
Functional Description .............................................................................................................................. 184
Synchronous ODT Mode ................................................................................................................................ 190
PDF: 09005aef859bddc0
4Gb_DDR3L_RS_F_EDJ.pdf - Rev. A 4/14 EN
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.



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