ECLAMP2342N Datasheet PDF - Semtech Corporation


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ECLAMP2342N
Semtech Corporation

Part Number ECLAMP2342N
Description ESD/EMI Protection
Page 6 Pages

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PROTECTION PRODUCTS - EMIClampTM
Description
The EClampTM2342N is a low pass filter array with
integrated TVS diodes. It is designed to suppress
unwanted EMI/RFI signals and provide electrostatic
discharge (ESD) protection in portable electronic
equipment. This state-of-the-art device utilizes solid-
state silicon-avalanche technology for superior clamp-
ing performance and DC electrical characteristics.
They have been optimized for protection of color
LCD panels in cellular phones and other portable
electronics.
The device consists of eight identical circuits comprised
of TVS diodes for ESD protection, and a resistor -
capacitor network for EMI/RFI filtering. A series
resistor value of 100and a capacitance value of
20pF are used to achieve 30dB minimum attenuation
from 1GHz to 2.5GHz. Each line features two stages of
TVS diode protection. The TVS diodes provide effec-
tive suppression of ESD voltages in excess of 15kV (air
discharge) and 8kV (contact discharge) per IEC 61000-
4-2, level 4.
The EClamp2342N is in a 16-pin, 0.5mm pitch QFN
package. It measures 3.0 x 3.0 x 1.0mm. The small
package makes it ideal for use in portable electronics
such as cell phones, digital still cameras, and PDA’s.
Features
EClamp2342N
ESD/EMI Protection
for Color LCD Interfaces
PRELIMINARY
‹ Bidirectional EMI/RFI filter with integrated TVS
for ESD protection
‹ ESD protection to IEC 61000-4-2 (ESD) Level4,
+/-15kV (air), +/-8kV (contact)
‹ Filter performance: 30dB minimum attenuation
1GHz to 2.5GHz
‹ TVS working voltage: 5V
‹ Resistor: 100Ω +/− 15%
‹ Input Capacitance: 20pF (VR = 0V)
‹ Protection and filtering for eight lines
‹ Solid-state technology
Mechanical Characteristics
‹ 16 pin QFN
‹ Nominal Dimensions: 3.0 x 3.0 x 1.0 mm
‹ Lead Pitch: 0.5mm
‹ Lead finish: Matte Tin
‹ Marking : Marking Code + Date Code
‹ Packaging : Tape and Reel per EIA 481
Applications
‹ Color LCD Panel Protection
‹ Cell Phone CCD Camera Lines
‹ Clamshell Cell Phones
‹ Personal Digital Assistants (PDA’s)
Circuit Diagram
Package Configuration
LOW PASS FILTER
16
1
R = 100, C=20pF (max)
Device Schematic (8X)
Revision 09/01/2004
www.DataSheet.in
16 Pin QFN (Top Side View)
Maximum Dimensions (in mm)
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PROTECTION PRODUCTS
Maximum Ratings
Rating
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Junction Temperature
Operating Temperature
Storage Temperature
Electrical Characteristics
Symbol
VESD
TJ
Top
TSTG
EClamp2342N
PRELIMINARY
Value
+/- 17
+/- 12
125
-40 to +85
-55 to +150
Units
kV
oC
oC
oC
Parameter
TVS Reverse Stand-Off Voltage
TVS Reverse Breakdown Voltage
TVS Reverse Leakage Current
Total Series Resistance
Total Capacitance
Symbol
VRWM
VBR
IR
R
Cin
Total Capacitance
Cin
Conditions
It = 1mA
VRWM = 3.0V
Each Line
Input to Gnd,
Each Line
VR = 0V, f = 1MHz
Input to Gnd,
Each Line
VR = 2.5V, f = 1MHz
Minimum
6
85
Ty p i cal
8
100
16
Maximum
5
10
0.5
115
20
Units
V
V
µA
Ohms
pF
12 pF
2004 Semtech Corp.
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PROTECTION PRODUCTS
Typical Characteristics
Typical Insertion Loss S21 (Each Line)
CH1 S21 LOG 6 dB / REF 0 dB
0 dB
-6 dB
-12 dB
-18 dB
-24 dB
-30 dB
-36 dB
-42 dB
1
2
1: -8.4313 dB
280.123 MHz
2: -18.865 dB
900 MHz
3: -31.170 dB
1.8 GHz
4: -31.638 dB
2.5 GHz
34
1
MHz
10
MHz
100
MHz
13
GHz GHz
START. 030 MHz
STOP 3000.000000 MHz
ESD Clamping (+8kV Contact)
EClamp2342N
PRELIMINARY
Analog Crosstalk (Each Line)
CH1 S21 LOG 20 dB /REF 0 dB
START. 030 MHz
STOP 3000.000000 MHz
ESD Clamping (-8kV Contact)
Capacitance vs. Reverse Voltage
(Normalized to 0 volts)
1.2
1
0.8
0.6
0.4
0.2
0
01
2004 Semtech Corp.
23
Reverse Voltage - VR (V)
f = 1 MHz
45
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3
Series Resistance vs. Temperature
(Normalized to 25 Degrees Celcius)
1.2
1.1
1.0
0.9
0.8
0.7
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Temperature (*C)
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EClamp2342N
PROTECTION PRODUCTS
Applications Information
Device Connection
The EClamp2342N is comprised of eight identical
circuits each consisting of a low pass filter for EMI/RFI
suppression and dual TVS diodes for ESD protection.
The device is housed in a 16-pin Quad Flat No-Lead
(QFN) package. Electrical connection is made via 16
pins located at the bottom of the device. A center tab
serves as the ground connection. Pin connections are
noted in the table to the right. The device is symmetri-
cal and designed for easy PCB routing as shown in the
layout example below. All path lengths should be kept
as short as possible to minimize the effects of parasitic
inductance in the board traces.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
Layout Example (Top Side View)
Outputs
1 2 3456 7 8
PRELIMINARY
Pin Identification and Configuration (Top Side View)
16 15 14 13
1 12
2 11
3 10
49
5678
Pin
3 - 10
1, 2, 11 - 16
Center Tab
Identification
Input, Lines 1, 2, 3, 4, 5, 6, 7, 8
Output Lines 1, 2, 3, 4, 5,6, 7, 8
Ground
Pin Configuration and Schematic
3
LOW PASS FILTER
27
LOW PASS FILTER
14
4
LOW PASS FILTER
18
LOW PASS FILTER
13
5
LOW PASS FILTER
16 9
LOW PASS FILTER
12
6
LOW PASS FILTER
15 10
LOW PASS FILTER
11
1 2 3 456 7 8
Inputs
I/O Lines 1 - 4
I/O Lines 5 - 8
2004 Semtech Corp.
www.DataSheet.in
4
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