DS64EV400 Datasheet PDF - National Semiconductor


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DS64EV400
National Semiconductor

Part Number DS64EV400
Description Programmable Quad Equalizer
Page 18 Pages

DS64EV400 datasheet pdf
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April 18, 2008
DS64EV400
Programmable Quad Equalizer
General Description
The DS64EV400 programmable quad equalizer provides
compensation for transmission medium losses and reduces
the medium-induced deterministic jitter for four NRZ data
channels. The DS64EV400 is optimized for operation up to
10 Gbps for both cables and FR4 traces. Each equalizer
channel has eight levels of input equalization that can be pro-
grammed by three control pins, or individually through a Serial
Management Bus (SMBus) interface.
The equalizer supports both AC and DC-coupled data paths
for long run length data patterns such as PRBS-31, and bal-
anced codes such as 8b/10b. The device uses differential
current-mode logic (CML) inputs and outputs. The
DS64EV400 is available in a 7 mm x 7 mm 48-pin leadless
LLP package. Power is supplied from either a 2.5V or 3.3V
supply.
Features
Equalizes up to 24 dB loss at 10 Gbps
Equalizes up to 22 dB loss at 6.4 Gbps
8 levels of programmable equalization
Settable through control pins or SMBus interface
Operates up to 10 Gbps with 30” FR4 traces
Operates up to 6.4 Gbps with 40” FR4 traces
0.175 UI residual deterministic jitter at 6.4 Gbps with 40”
FR4 traces
Single 2.5V or 3.3V power supply
Signal Detect for individual channels
Standby mode for individual channels
Supports AC or DC-Coupling with wide input common-
mode
Low power consumption: 375 mW Typ at 2.5V
Small 7 mm x 7 mm 48-pin LLP package
9 kV HBM ESD Rating
-40 to 85°C operating temperature range
Simplified Application Diagram
© 2008 National Semiconductor Corporation 300320
30032024
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Pin Name Pin #
I/O, Type
HIGH SPEED DIFFERENTIAL I/O
IN_0+
1 I, CML
IN_0–
2
IN_1+
IN_1–
4 I, CML
5
IN_2+
IN_2–
8 I, CML
9
IN_3+
IN_3–
11 I, CML
12
OUT_0+
OUT_0–
36 O, CML
35
OUT_1+
OUT_1–
33 O, CML
32
OUT_2+
OUT_2–
29 O, CML
28
OUT_3+
OUT_3–
26 O, CML
25
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
37 I, LVCMOS
14
23
DEVICE CONTROL
EN0 44 I, LVCMOS
EN1 42 I, LVCMOS
EN2 40 I, LVCMOS
EN3 38 I, LVCMOS
FEB 21 I, LVCMOS
SD0
SD1
SD2
SD3
POWER
VDD
GND
DAP
45 O, LVCMOS
43 O, LVCMOS
41 O, LVCMOS
39 O, LVCMOS
3, 6, 7,
10, 13,
15, 46
22, 24,
27, 30,
31, 34
PAD
Power
Power
Power
Description
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 6.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 6.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 6.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 6.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50
terminating resistor connects OUT_0+ to VDD and OUT_0- to VDD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50
terminating resistor connects OUT_1+ to VDD and OUT_1- to VDD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50
terminating resistor connects OUT_2+ to VDD and OUT_2- to VDD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50
terminating resistor connects OUT_3+ to VDD and OUT_3- to VDD.
BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is
internally pulled high. BST_1 and BST_0 are internally pulled low.
Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0]
pins. When held low, the equalizer boost setting is controlled by SMBus (see Table 1) register
bits. FEB is internally pulled High.
Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.
Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.
VDD = 2.5V ± 5% or 3.3V ± 10%. VDD pins should be tied to VDD plane through low inductance
path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes.
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board.
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Pin Name Pin #
I/O, Type
SwEwRwI.ADLatMaSAhNeAetG4UE.McoEmNT BUS (SMBus) INTERFACE CONTROL PINS
Description
SDA
18 I/O, LVCMOS Data input/output (bi-directional). Internally pulled high.
SDC
17 I, LVCMOS Clock input. Internally pulled high.
CS 16 I, LVCMOS Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When
pulled low, access to the equalizer SMBus registers are disabled. Please refer to “SMBus
configuration Registers” section for detail information.
Other
Reserv
19, 20
Reserved. Do not connect.
47,48
Note: I = Input O = Output
Connection Diagram
Ordering Information
NSID
DS64EV400SQ
DS64EV400SQX
Package Type, Qty Size
48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 250
48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 2500
30032026
Package ID
SQA48D
SQA48D
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www.DataShAeebt4Us.ocolmute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
CMOS Input Voltage
CMOS Output Voltage
CML Input/Output Voltage
−0.5V to +4.0V
−0.5V + 4.0V
−0.5V to 4.0V
−0.5V to 4.0V
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4
Seconds)
+150°C
−65°C to +150°C
+260°C
ESD Rating
HBM, 1.5 k, 100 pF
CML Inputs
Thermal Resistance
 θJA, No Airflow
> 9 kV
> 250V
30°C/W
Recommended Operating
Conditions
Supply Voltage (note 9)
VDD2.5 to GND
VDD3.3 to GND
Ambient Temperature
Min
2.375
3.0
−40
Typ Max Units
2.5 2.625 V
3.3 3.6 V
25 +85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(note 2)
Max
POWER
P
Power Supply Consumption
Device Output Enabled
(EN [0–3] = High), VDD3.3
Device Output Disable
(EN [0–3] = Low), VDD3.3
P
Power Supply Consumption
Device Output Enabled
(EN [0–3] = High), VDD2.5
Device Output Disable
(EN [0–3] = Low), VDD2.5
N Supply Noise Tolerance (Note 4) 50 Hz — 100 Hz
100 Hz — 10 MHz
10 MHz — 1.6 GHz
490 700
100
360 490
30
100
40
10
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
VDD3.3
2.0
VDD2.5
1.6
VIL Low Level Input Voltage
-0.3
VOH
High Level Output Voltage
IOH = -3mA, VDD3.3
2.4
IOH = -3mA, VDD2.5
2.0
VOL
Low Level Output Voltage
IOL = 3mA
IIN Input Leakage Current VIN = VDD
VIN = GND
-15
IIN-P
Input Leakage Current with
VIN = VDD, with internal pull-down
Internal Pull-Down/Up Resistors resistors
VDD3.3
VDD2.5
0.8
0.4
+15
+120
VIN = GND, with internal pull-up
resistors
-20
SIGNAL DETECT
SDH
Signal Detect ON Threshold Level Default input signal level to assert
SD pin, 6.4 Gbps
70
SDI
Signal Detect OFF Threshold
Default input signal level to de-
Level
assert SD, 6.4 Gbps
40
Units
mW
mW
mW
mVP-P
mVP-P
mVP-P
V
V
V
V
V
μA
μA
μA
μA
mVp-p
mVp-p
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