DAC1627D1G25 Datasheet PDF - NXP Semiconductors

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DAC1627D1G25
NXP Semiconductors

Part Number DAC1627D1G25
Description Dual 16-bit DAC
Page 30 Pages


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DAC1627D1G25
Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and
x8 interpolating
Rev. 1 — 29 April 2011
Objective data sheet
1. General description
The DAC1627D1G25 is a high-speed 16-bit dual channel Digital-to-Analog Converter
(DAC) with selectable ×2, ×4 and ×8 interpolating filters optimized for multi-carrier and
broadband wireless transmitters at sample rates of up to 1.25 Gsps. Supplied from a
3.3 V and a 1.8 V source, the DAC1627D1G25 integrates a differential scalable output
current up to 31.8 mA.
The DAC1627D1G25 is capable of meeting multi-carrier GSM specifications. For
example, with an output frequency of 150 MHz and a DAC clock frequency of 1.22 Gsps
the full-scale dynamic range is:
SFDRRBW = 85 dBc (bandwidth = 250 MHz)
IMD3 = 85 dBc
The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1G25.
The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data
Rate (DDR) receiver interface, with an on-chip 100 Ω termination. The LVDS DDR
interface accepts a multiplex input data stream such as interleaved or folded. An internal
LVDS input auto-calibration ensures the robustness and stability of the interface.
http://www.DataSheet4U.net/
Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. The
mixer frequency is set by a 40-bit Numerically Controlled Oscillator (NCO). High resolution
internal gain, phase and offset control provide outstanding image and Local Oscillator
(LO) signal rejection at the system analog modulator output.
An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at
the DAC output.
Multiple device synchronization allows synchronization of the outputs of multiple DAC
devices. MDS guarantees a maximum skew of one output clock period between several
devices.
The DAC1627D1G25 includes a very low noise capacitor-free integrated Phase-Locked
Loop (PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.
The DAC1627D1G25 is available in a HVQFN72 package (10 mm × 10 mm).
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NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
2. Features and benefits
„ Dual 16-bit resolution
„ Synchronization of multiple DAC
devices
„ 1.25 Gsps maximum update rate
„ 3 or 4 wires mode SPI interface
„ Selectable ×2, ×4 and ×8 interpolation „ Differential scalable output current from
filters
6.95 mA to 31.8 mA
„ Very low noise capacitor-free integrated „ External analog offset control
Phase-Locked Loop (PLL)
(10-bit auxiliary DACs)
„ Embedded Numerically Controlled
„ High resolution internal digital gain and
Oscillator (NCO) with 40-bit
offset control to support high
programmable frequency
performance IQ-modulator image
rejection
„ Embedded complex modulator
„ Internal phase correction
„ 1.8 V and 3.3 V power supplies
„ Inverse (sin x) / x function
„ LVDS DDR compatible input interface „ Power-down mode and Sleep mode;
with on-chip 100 Ω terminations
5-bit NCO low power mode
„ LVDS DDR input clock up to 312.5 MHz „ On-chip 1.25 V reference
„ LVDS or LVPECL compatible DAC clock „ Industrial temperature range 40 °C to
+85 °C
„ Interleaved or folded I and Q data input „ 72 pins small form factor HVQFN
mode
package
3. Applications
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„ Wireless infrastructure: MG_GSM, LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
„ Communication: LMDS/MMDS, point-to-point
„ Direct Digital Synthesis (DDS)
„ Broadband wireless systems
„ Digital radio links
„ Instrumentation
„ Automated Test Equipment (ATE)
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
DAC1627D1G25 HVQFN72 plastic thermal enhanced very thin quad flat package; no leads;
72 terminals; body 10 × 10 × 0.85 mm
Version
SOT813-3
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
2 of 69
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5. Block diagram
DAC1627D
SDO SDIO SCS_N SCLK
DCMSU
SPI
NCO
40-bit frequency setting
16-bit phase adjustment
cos sin
ALIGNP
ALIGNN
LD(15)P to
LD(0)P
LD(15)N to
LD(0)N
LDCLKP
LDCLKN
FIR 1
FIR 2
x2 x2
16
LVDS
DDR/
DIF
CDI
MDS
COARSE
16
FIR 1
FIR 2
x2 x2
FIR 3
x2
FIR 3
x2
+
-
+
+
CLKP
CLKN
MDSP
MDSN
CLOCK GENERATOR/PLL
MULTI-DAC
SYNCHRONIZATION
COMPLEX MODULATOR
Fig 1. Block diagram
RESET_N
10-BIT
OFFSET
CONTROL
AUX.
DAC
X
sin X
10-BIT
ANALOG GAIN
CONTROL
PHASE
COMP +
DAC A
AUXAP
AUXAN
IOUTAP
IOUTAN
OFFSET
CONTROL
REF.
BANDGAP
AND
BIASING
GAPOUT
VIRES
X
sin X
PHASE +
COMP
DAC B
10-BIT
ANALOG GAIN
CONTROL
10-BIT
OFFSET
CONTROL
AUX.
DAC
IOUTBP
IOUTBN
AUXBP
AUXBN
001aan827



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6. Pinning information
6.1 Pinning
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
terminal 1
index area
CLKP 1
CLKN 2
MDSP 3
MDSN 4
TM 5
ALIGNP 6
ALIGNN 7
LD[15]P 8
LD[15]N 9
LD[14]P 10
LD[14]N 11
VDDD(1V8) 12
LD[13]P 13
LD[13]N 14
LD[12]P 15
LD[12]N 16
LD[11]P 17
LD[11]N 18
DAC1627D1G25
http://www.DataSheet4U.net/
54 RESET_N
53 SCS_N
52 SCLK
51 SDIO
50 SDO
49 IO0
48 IO1
47 LD[0]N
46 LD[0]P
45 LD[1]N
44 LD[1]P
43 VDDD(1V8)
42 LD[2]N
41 LD[2]P
40 LD[3]N
39 LD[3]P
38 LD[4]N
37 LD[4]P
001aan828
Fig 2. Pin configuration
Transparent top view
6.2 Pin description
Table 2.
Symbol
CLKP
CLKN
MDSP
MDSN
TM
ALIGNP
ALIGNN
LD[15]P
LD[15]N
Pin description
Pin Type[1]
1I
2I
3 IO
4 IO
5I
6I
7I
8I
9I
Description
DAC clock positive input
DAC clock negative input
multi-device synchronization positive signal
multi-device synchronization negative signal
Test mode selection (connect to GND)
positive input for data alignment
negative input for data tanglement
LVDS positive input bit 15[2]
LVDS negative input bit 15[2]
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
4 of 69
datasheet pdf - http://www.DataSheet4U.net/



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NXP Semiconductors
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