CYU01M16ZFC Datasheet PDF - Cypress Semiconductor

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CYU01M16ZFC
Cypress Semiconductor

Part Number CYU01M16ZFC
Description 16-Mbit (1M x 16) Pseudo Static RAM
Page 14 Pages


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PRELIMINARY
CYU01M16ZFC
MoBL3™
16-Mbit (1M x 16) Pseudo Static RAM
Features
• Wide voltage range: 1.7V–1.95V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• 16-word Page Mode
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Deep Sleep Mode
• Offered in a Lead-Free 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
Functional Description[1]
The CYU01M16ZFC is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE LOW) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7), is written into the location specified on the address pins
(A0 through A19). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A19).
Reading from the device is accomplished by taking Chip
Enables (CE LOW) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O8 to
I/O15. Refer to the truth table for a complete description of read
and write modes.
Deep Sleep Mode is enabled by driving ZZ LOW. See the Truth
Table for a complete description of Read, Write, and Deep
Sleep mode.
Logic Block Diagram
DATA IN DRIVERS
A
A
8
9
A10
A11
A12
A13
1M × 16
RAM Array
A14
AA1156
AAA111987
COLUMN DECODER
I/O0–I/O7
I/O8–I/O15
Power-Down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE
ZZ
CE
Refresh/Power-down
Circuit
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
www.DDaotacSuhmeeetn4Ut #.n:e3t 8-05604 Rev. *F
Revised January 16, 2006



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Pin Configuration[2, 3]
PRELIMINARY
VFBGA
Top View
12 3 4
56
BLE OE A0 A1 A 2 ZZ
I/O8 BHE A3 A4 CE I/O0
I/O9 I/O10 A5 A6 I/O1 I/O2
VSS I/O11 A17 A7 I/O3 VCC
VCC I/O12 NC
A16 I/O4 VSS
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 A19
A12 A13 WE
I/O7
A18 A8 A9 A10 A11
NC
A
B
C
D
E
F
G
H
CYU01M16ZFC
MoBL3™
Product Portfolio[4]
Product
CYU01M16ZFC
VCC Range (V)
Min.
Typ.[4]
Max.
1.7 1.8 1.95
Speed
(ns)
70
Power Dissipation
Operating ICC (mA)
f = 1MHz
Typ.[4] Max.
f = fmax
Typ.[4] Max.
Standby ISB2 (µA)
Typ.[4] Max.
3 5 18 25 55 70
Low-Power Modes
At power-up, all four sections of the die are activated and the
PSRAM enters into its default state of full memory size and
refresh space. This device provides four different Low-Power
Modes.
1. Reduced Memory Size Operation
2. Partial Array Refresh
3. Deep Sleep Mode
4. Temperature Controlled Refresh
Reduced Memory Size Operation
In this mode, the 16 Mb PSRAM can be operated as a 12-Mbit,
8-Mbit or a 4-Mbit memory block. Please refer to “Variable
Address Space Register (VAR)” on page 4 for the protocol to
turn on/off sections of the memory. The device remains in RMS
mode until changes to the Variable Address Space register are
made to revert back to a complete 16-Mbit PSRAM.
Partial Array Refresh
The Partial Array Refresh mode allows customers to turn off
sections of the memory block in the Stand-by mode (with ZZ
tied low) to reduce standby current. In this mode the PSRAM
will only refresh certain portions of the memory in the Stand-By
Mode, as configured by the user through the settings in the
Variable Address Register.
Once ZZ returns high in this mode, the PSRAM goes back to
operating in full address refresh. Please refer to “Variable
Address Space Register (VAR)” on page 4 for the protocol to
turn off sections of the memory in Stand-By mode. If the VAR
register is not updated after the power up, the PSRAM will be
in its default state. In the default state the whole memory array
will be refreshed in the Stand-By Mode. The 16-Mbit MoBL3 is
divided into four 4-Mbit sections allowing certain sections to be
active (i.e., refreshed).
Deep Sleep Mode
In this mode, the data integrity in the PSRAM is not
guaranteed. This mode can be used to lower the power
consumption of the PSRAM in an application. This mode can
be enabled and disabled through VAR similar to the RMS and
PAR mode. Deep Sleep Mode is activated by driving ZZ LOW.
The device stays in the deep sleep mode until ZZ is driven
HIGH.
Notes:
2. Ball H6, E3 can be used to upgrade to 32M and 64M density respectively.
3. NC “no connect” - not connected internally to the die.
4.
Typical values are included for reference only and are not
after any design changes that may affect the parameter.
guaranteed
or
tested.
Typical
values
are
measured
at
VCC
=
VCC(typ.),
TA
=
25°C.
Tested
initially
and
Document #: 38-05604 Rev. *F
Page 2 of 14



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PRELIMINARY
CYU01M16ZFC
MoBL3™
Variable Address Mode Register (VAR) Update[5, 6]
ADDRESS
tWC
Lower-order address (A0-A4) Low Power Modes
CE
BHE / BLE
WE
ZZ
tSA
t ZZWE
Deep Sleep Mode—Entry/Exit [7]
ZZ
CE
t CDR
tAW
tBW
t PWE
tZZMIN
t ZZMIN
Deep Sleep Mode
tR
tHA
VAR Update and Deep Sleep Mode Timing[5, 6]
Parameter
Description
tZZWE
ZZ LOW to Write Start
tCDR
tR[7]
Chip deselect to ZZ LOW
Operation Recovery Time (Deep Sleep Mode only)
tZZMIN
Deep Sleep Mode Time
Notes:
5. OE and the data pins are in a don’t care state while the device is in variable address mode.
6. All other timing parameters are as shown in the data sheets.
7. tR applies only in the deep sleep mode.
Min.
0
200
8
Max.
1
Unit
µs
ns
µs
µs
Document #: 38-05604 Rev. *F
Page 3 of 14



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PRELIMINARY
VI ariable Address Space Register (VAR)
CYU01M16ZFC
MoBL3™
A19–A5
A4 A3 A2 A1 A0
Memory Array Selection
00 – 16M(Default)
01 – 12M
10 – 8M
11 – 4M
Reserved
Top/Bottom Half Selection
0 – Bottom (Default)
1 – Top
Array On/Off on ZZ
ZZ Enable/Disable 0 – PAR Mode (Default)
0 – Deep Sleep Enabled (Default) 1 – RMS Mode
1 – Deep Sleep Disabled
Variable Address Space—Address Patterns
Partial Array Refresh Mode (A3 = 0, A4 = 1)
A2 A1, A0
Refresh Section
0 1 1 1/4th of the array
0 1 0 1/2th of the array
0 0 1 3/4th of the array
1 1 1 1/4th of the array
1 1 0 1/2th of the array
1 0 1 3/4th of the array
Address
00000h - 3FFFFh (A19 = A18 = 0)
00000h - 7FFFFh (A19 = 0)
00000h - BFFFFh (A19:A18 not equal to 1 1)
C0000h - FFFFFh (A19 = A18= 1)
80000h - FFFFFh (A19 = 1)
40000h - FFFFFh (A19:A18 not equal to 0 0)
0 1 1 1/4th of the array
0 1 0 1/2th of the array
0 0 1 3/4th of the array
Reduced Memory Size Mode (A3 = 1, A4 = 1)
00000h - 3FFFFh (A19 = A18 = 0)
00000h - 7FFFFh (A19 = 0)
00000h - BFFFFh (A19:A18 not equal to 1 1)
0 0 0 Full array
1 1 1 1/4th of the array
1 1 0 1/2th of the array
1 0 1 3/4 h of the array
00000h - FFFFFh (Default)
C0000h - FFFFFh (A19 = A18 = 1)
80000h - FFFFFh (A19 = 1)
40000h - FFFFFh (A19:A18 not equal to 0 0)
1 0 0 Full array
00000h - FFFFFh (Default)
Size
256K x 16
512K x 16
768K x 16
256K x 16
512K x16
786K x16
Density
4M
8M
12M
4M
8M
12M
256K x 16
512K x 16
768K x 16
1M x 16
256K x 16
512K x 16
768K x 16
1M x 16
4M
8M
12M
16M
4M
8M
12M
16M
Page Mode
This device can be operated in a page read mode. This is
accomplished by initiating a normal read of the device.
In order to operate the device in page mode, the upper order
address bits should be fixed for four-word page access
operation, all address bits except for A1 and A0 should be
fixed until the page access is completed. For an eight-word
page access, all address bits, except for A2, A1, and A0,
should be fixed. For a sixteen-word page mode all address
bits, except for A3, A2, A1, and A0, should be fixed.
The supported page lengths are four, eight, and sixteen words.
Random page read is supported for all three four, eight, and
sixteen-word page read options. Therefore, any address can
be used as the starting address.
Please, refer to the table below for an overview of the page
read modes.
Page Mode Feature
Page Length
Page Read Corresponding Addresses
Page Read Start Address
Page Direction
4-Word Mode
4 words
A1, A0
Don't Care
Don't Care
8-Word Mode
8 words
A2, A1, A0
Don't Care
Don't Care
16-Word Mode
16 words
A3, A2, A1, A0
Don’t Care
Don’t Care
Document #: 38-05604 Rev. *F
Page 4 of 14



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