CYU01M16SCG Datasheet PDF - Cypress Semiconductor

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CYU01M16SCG
Cypress Semiconductor

Part Number CYU01M16SCG
Description 16-Mbit (1M x 16) Pseudo Static RAM
Page 11 Pages


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PRELIMINARY
CYU01M16SCG
MoBL3™
16-Mbit (1M x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.2V–3.6V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
Functional Description[1]
The CYU01M16SCG is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
Logic Block Diagram
DATA IN DRIVERS
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE1 HIGH or
CE2 LOW or both BHE and BLE are HIGH). The input/output
pins (I/O0 through I/O15) are placed in a high-impedance state
when: deselected (CE1 HIGH or CE2 LOW), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE1 LOW and CE2 HIGH and WE LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A19). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and
CE2 HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15.
Refer to the truth table for a complete description of read and
write modes.
A8
A9
A10
A11
A12 1M x 16
A13
A14
RAM Array
A15
A16
A17
A18
A19
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power -Down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE2
CE1
CE2
CE1
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
www.DDaotacSuhmeeetn4Ut #.n:e0t 01-09739 Rev. **
Revised August 7, 2006
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PRELIMINARY
CYU01M16SCG
MoBL3™
Pin Configuration[2, 3]
48-Ball VFBGA
Top View
12
34
56
BLE OE A0 A1 A2 CE2
A
I/O8 BHE A3 A4 CE1 I/O0
I/O9 I/O10 A5 A6 I/O1 I/O2
B
C
VSS I/O11 A17 A7 I/O3 VCC
D
VCC I/O12 NC
A16 I/O4 VSS
I/O14 I/O13 A14 A15 I/O5 I/O6
E
F
I/O15 A19 A12 A13 WE I/O7
G
A18 A8 A9 A10 A11 NC H
Product Portfolio[4]
Product
CYU01M16SCG
VCC Range (V)
Min.
Typ.[4]
Max.
2.2 3.0 3.6
Speed
(ns)
70
Power Dissipation
Operating ICC (mA)
f = 1MHz
Typ.[4] Max.
f = fmax
Typ.[4] Max.
Standby ISB2 (µA)
Typ.[4] Max.
3 5 18 25 55 70
Power-up Characteristics
The initialization sequence is shown in the figure below. Chip
Select should be CE1 HIGH or CE2 LOW for at least 200 µs
after VCC has reached a stable value. No access must be
attempted during this period of 200 µs.
Stable Power
VCC
Tpu
CE
First Access
Parameter
Tpu
Description
Chip Enable Low After Stable VCC
Min.
200
Typ.
Max.
Unit
µs
Notes:
2. Ball H6 and E3 can be used to upgrade to a 32-Mbit and a 64-Mbit density, respectively.
3. NC “no connect” - not connected internally to the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25°C. Tested initially
and after design changes that may affect the parameters.
Document #: 001-09739 Rev. **
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PRELIMINARY
CYU01M16SCG
MoBL3™
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to
Ground Potential ..............................–0.3V to VCCMAX + 0.3V
DC Voltage Applied to Outputs
in High Z State[5, 6, 7]........................–0.3V to VCCMAX + 0.3V
DC Input Voltage[5, 6, 7].................... –0.3V to VCCMAX + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... > 200 mA
Device
CYU01M16SCG
Operating
Range Temperature (TA)
Industrial –40°C to +85°C
VCC
2.2V to
3.6V
DC Electrical Characteristics (Over the Operating Range)[5, 6, 7]
Parameter
Description
Test Conditions
CYU01M16SCG-70 ns
Min.
Typ.[4]
Max.
VCC Supply Voltage
VOH Output HIGH Voltage IOH = –0.1 mA
VCC= 2.2V to 3.6V
VOL Output LOW Voltage IOL = 0.1 mA
VCC= 2.2V to 3.6V
VIH Input HIGH Voltage VCC= 2.2V to 3.6V
VIL Input LOW Voltage VCC= 2.2V to 3.6V
IIX
Input Leakage
GND < VIN < VCC
Current
2.2
VCC – 0.2
3.0
3.6
0.2
0.8 * VCC
–0.3
–1
VCC + 0.3V
0.2 * VCC
+1
IOZ
Output Leakage
GND < VOUT < VCC
Current
–1 +1
ICC
VCC Operating
f = fMAX = 1/tRC VCC= VCCmax
Supply
IOUT = 0 mA
Current
CMOS levels
18 25
f = 1MHz
35
ISB1
Automatic CE
CE1 > VCC – 0.2V, CE2 < 0.2V,
Power-Down
VIN > VCC – 0.2V, VIN < 0.2V, f = fMAX
Current—CMOS (Address and Data Only), f = 0
Inputs
(OE, WE, BHE and BLE), VCC = 3.60V
ISB2
Automatic CE
CE1 > VCC – 0.2V, CE2 < 0.2V,
Power-Down
VIN > VCC – 0.2V or
Current—CMOS
VIN < 0.2V,
Inputs
f = 0, VCC=VCCMAX
55 70
55 70
Capacitance[8]
Unit
V
V
V
V
V
µA
µA
mA
mA
µA
µA
Parameter
Description
CIN
COUT
Input Capacitance
Output Capacitance
Thermal Resistance[8]
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max.
8
8
Unit
pF
pF
Parameter
Description
Test Conditions
ΘJA Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods
ΘJC
Thermal Resistance (Junction to Case)
and procedures for measuring thermal
impedence, per EIA/JESD51
Notes:
5. VIL(MIN) = –0.5V for pulse durations less than 20 ns.
6. VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns.
7. Overshoot and undershoot specifications are characterized and are not 100% tested.
8. Tested initially and after any design or process changes that may affect these parameters.
VFBGA
56
11
Unit
°C/W
°C/W
Document #: 001-09739 Rev. **
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PRELIMINARY
CYU01M16SCG
MoBL3™
AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
VCC
GND
10%
90%
90%
10%
R2 Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
R1
R2
RTH
VTH
3.0V (VCC)
26000
26000
13000
1.50
Unit
V
Switching Characteristics Over the Operating Range[9, 10, 11, 14, 15]
70 ns
Parameter
Description
Min.
Max.
Unit
Read Cycle
tRC[13]
Read Cycle Time
70 40000
ns
tCD Chip Deselect Time CE1 = HIGH or
CE2 =LOW, BLE/BHE High Pulse Time
15
ns
tAA Address to Data Valid
70 ns
tOHA
Data Hold from Address Change
5
ns
tACE
CE LOW to Data Valid
70 ns
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[10, 11, 12]
OE HIGH to High Z[10, 11, 12]
CE LOW to Low Z[10, 11, 12]
CE HIGH to High Z[10, 11, 12]
35
5
25
10
25
ns
ns
ns
ns
ns
tDBE
tLZBE
tHZBE
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z[10, 11, 12]
BLE/BHE HIGH to High Z[10, 11, 12]
70
5
25
ns
ns
ns
Notes:
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ.)/2, input pulse levels
of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
10. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V).
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. If invalid address signals shorter than min.tRC are continuously repeated for 40 µs, the device needs a normal read timing (tRC) or needs to enter standby state
at least once in every 40 µs.
14. In order to achieve 70-ns performance, the read access must be Chip Enable (CE1 or CE2) controlled. That is, the addresses must be stable prior to Chip Enable
going active.
Document #: 001-09739 Rev. **
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