CYF2072V Datasheet PDF - Cypress Semiconductor

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CYF2072V
Cypress Semiconductor

Part Number CYF2072V
Description 18/36/72-Mbit Programmable Multi-Queue FIFOs
Page 30 Pages


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CYF2018V, CYF2036V
CYF2072V
18/36/72-Mbit Programmable
Multi-Queue FIFOs
18/36/72-Mbit Programmable Multi-Queue FIFOs
Features
Memory organization
Industry’s largest first in first out (FIFO) memory densities:
18-Mbit, 36-Mbit and 72-Mbit
Selectable memory organization: × 9, × 12, × 16, × 18, × 20,
× 24, × 32, × 36
Up to 100-MHz clock operation
Unidirectional operation
Independent read and write ports
Supports simultaneous read and write operations
Reads and writes operate on independent clocks upto a
maximum ratio of two enabling data buffering across clock
domains
Supports multiple I/O voltage standard: Low voltage
complementary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
Input and output enable control for write mask and read skip
operations
User configured multi-queue operating mode upto 8-queues
Mark and retransmit: resets read pointer to user marked
position
Empty and full flags
Flow-through mailbox register to send data from input to output
port, bypassing the FIFO sequence
Configure programmable flags and registers through serial or
parallel modes
Separate serial clock (SCLK) input for serial programming
Master reset to clear entire FIFO
Joint test action group (JTAG) port provided for boundary scan
function
Industrial temperature range: –40 °C to +85 °C
Functional Description
The Cypress programmable FIFO family offers the industry’s
highest-density programmable FIFO memory device. It has
independent read and write ports, which can be clocked up to
100 MHz. User can configure input and output bus sizes. The
maximum bus size of 36 bits enables a maximum data
throughput of 3.6 Gbps. The read and write ports can support
multiple I/O voltage standards. The user-programmable
registers enable user to configure the device operation as
desired. The device also offers a simple and easy-to-use
interface to reduce implementation and debugging efforts,
improve time-to-market, and reduce engineering costs. This
makes it an ideal memory choice for a wide range of applications
including multiprocessor interfaces, video and image
processing, networking and telecommunications, high-speed
data acquisition, or any system that needs buffering at very high
speeds across different domains.
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. The data is sequentially
written into the FIFO from the write port. If the writes and inputs
are enabled, the data on the write port gets written into the device
at the rising edge of the write clock. Enabling the reads and
outputs fetches data on the read port at every rising edge of the
read clock. Both reads and writes can occur simultaneously at
different speeds provided the ratio of read to write clock is in the
range of 0.5 to 2. Appropriate flags are set whenever the FIFO
is empty or full.
The device also supports multi-queue operation upto 8 queues,
mark and retransmit of data, and a flow-through mailbox register.
All product features and specs are common to all densities
(CYF2072V, CYF2036V, and CYF2018V) unless otherwise
specified. All descriptions are given assuming the device is
CYF2072V operated in × 36 mode. They hold good for other
densities (CYF2036V, and CYF2018V) and all port sizes × 9,
× 12, × 16, × 18, × 20, × 24 and × 32 unless otherwise specified.
The only difference will be in the input and output bus width.
Table 1 on page 8 shows the part of bus with valid data from
D[35:0] and Q[35:0] in × 9, × 12, × 16, × 18, × 20, × 24, × 32 and
× 36 modes.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4NUu.nmebt er: 001-68336 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 12, 2011
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Logic Block Diagram
CYF2018V, CYF2036V
CYF2072V
Document Number: 001-68336 Rev. **
Page 2 of 30
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CYF2018V, CYF2036V
CYF2072V
Contents
Pin Diagram for CYF2XXXV ............................................. 4
Pin Definitions .................................................................. 5
Architecture ...................................................................... 7
Reset Logic ................................................................. 7
Flag Operation ............................................................. 7
Full Flag ....................................................................... 7
Empty Flag .................................................................. 7
Retransmit from Mark Operation ................................. 7
Flow-through mailbox Register .................................... 7
Selecting Word Sizes .................................................. 7
Data Valid Signal (DVal) .............................................. 8
Queue Valid Signal (QVal[2:0]) ................................... 8
Power Up ........................................................................... 8
Write Mask and Read Skip Operation ......................... 9
Multi-Queue Operation ................................................ 9
Width Expansion Configuration ................................. 11
Memory Organization for Different Port Sizes ........... 11
Read/Write Clock Requirements ............................... 12
JTAG operation ............................................................... 13
Maximum Ratings ........................................................... 14
Operating Range ............................................................. 14
Recommended DC Operating Conditions .................... 14
Electrical Characteristics ............................................... 14
I/O Characteristics .......................................................... 15
Latency Table .................................................................. 15
Switching Characteristics .............................................. 16
Switching Waveforms .................................................... 17
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC Solutions ......................................................... 30
Document Number: 001-68336 Rev. **
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CYF2018V, CYF2036V
CYF2072V
G
Pin Diagram for CYF2XXXV
1
A FF
B EF
C D4
D D6
E D8
F D10
G D12
H D14
J D16
K DNU
L D18
M D20
N D22
P D24
R D26
T D28
U DVal
V QVal1
W TDO
2
D0
D2
D5
D7
D9
D11
D13
D15
D17
DNU
D19
D21
D23
D25
D27
D29
DNU
QVal0
QVal2
34
D1 WQSEL0
D3 WQSEL1
WEN WQSEL2
VSS VCC1
VCC2 VCC2
VSS VSS
VCC2 VCC2
VSS VSS
VCC2 VCC2
WCLK DNU
VCC2 VCC2
VSS VSS
VCC2 VCC2
VSS VSS
VCC2 VCC2
VSS VCC1
D30 D31
D32 D33
D34 D35
Figure 1. 209-ball FBGA (Top View)
5 6 78
PORTSZ0 PORTSZ1
DNU RQSEL0
DNU
PORTSZ2
DNU RQSEL1
VCC1
DNU
VCC1 RQSEL2
DNU
LD
DNU
VCC1
VCCIO
VCCIO
VCCIO VCC2
VSS
DNU
VSS
VSS
VCCIO
VCC1
VCCIO VCC2
VSS
VCC1
VSS
VSS
VCCIO
VCC1
VCCIO VCC2
VSS
IE
VSS
DNU
VCCIO
VCC1
VCCIO VCC2
VSS
VCC1
VSS
VSS
VCCIO
VCC1
VCCIO VCC2
VSS
SPI_SEN
VSS
VSS
VCCIO
VCCIO
VCCIO VCC2
VCC1
SPI_SI
VCC1
VCC1
DNU
DNU
SPI_SCLK Vref
DNU
MRS
MB DNU
TDI
TRST
TMS
TCK
9
RT
REN
RCLK
VSS
VCC2
VSS
VCC2
VSS
VCC2
VCCIO
VCC2
VSS
VCC2
VSS
VCC2
VSS
OE
MARK
Vref
10
Q0
Q2
Q4
Q6
Q8
Q10
Q12
Q14
Q16
VCCIO
Q18
Q20
Q22
Q24
Q26
Q28
Q30
Q32
Q34
11
Q1
Q3
Q5
Q7
Q9
Q11
Q13
Q15
Q17
VCCIO
Q19
Q21
Q23
Q25
Q27
Q29
Q31
Q33
Q35
Document Number: 001-68336 Rev. **
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Cypress Semiconductor
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