CYDMX256B16 Datasheet PDF - Cypress Semiconductor

www.Datasheet-PDF.com

CYDMX256B16
Cypress Semiconductor

Part Number CYDMX256B16
Description 16 K/8 K/4 K x 16 MoBL ADM 16 K/8 K/4 K x 16 MoBL ADM
Page 25 Pages


CYDMX256B16 datasheet pdf
Download PDF
CYDMX256B16 pdf
View PDF for Mobile

No Preview Available !

CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
16 K/8 K/4 K × 16 MoBL® ADM
Asynchronous Dual-Port Static RAM
16 K/8 K/4 K × 16 MoBL® ADM Asynchronous Dual-Port Static RAM
Features
True dual-ported memory block that allow simultaneous
independent access
One port with dedicated time multiplexed address and data
(ADM) interface
One port configurable to standard SRAM or time multiplexed
address and data interface
16 K/8 K/4 K × 16 memory configuration
High speed access
65 ns or 90 ns ADM interface
40 ns or 60 ns standard SRAM interface
Fully asynchronous operation
Port independent 1.8 V, 2.5 V, and 3.0 V IOs
Block Diagram
Ultra low operating power
Active: ICC = 15 mA (typical) at 90 ns
Active: ICC = 25 mA (typical) at 65 ns
Standby: ISB3 = 2 A (typical)
Port independent power down
On-chip arbitration logic
Mailbox interrupt for port to port communication
Input Read and Output Drive registers
Upper byte and lower byte control
Small package: 6 × 6 mm, 100-ball Pb-free BGA
Industrial temperature range
SFEN#
IRR/ODR
IRR1-IRR0 [note 2]
ODR4-ODR0
I/OL15-I/OL8
I/OL7-I/OL0
ADV#L
UB#L
LB#L
Mux'ed
Address /
Data
I/O Control
DataL<15..0>
AddrL<13..0>
Dual Ported
Memory Array
16k/8k/4k x 16
DataR<15..0>
AddrR<13..0>
Mux'ed
Address/
Data
I/O Control
Address
Decode
Address
Decode
CS#L
OE#L
WE#L
BUSY#L
INT#L
Control Logic
CS#R
OE#R
WE#R
BUSY#R
INT#R
I/OR15-I/OR8
I/OR7-I/OR0
ADV#R
UB#R
LB#R
A13-A0 [note 1]
MSEL
Notes
1. A13-A0 for CYDMX256A16 and CYDMX256B16; A12-A0 for CYDMX128A16 and CYDMX128B16; and A11-A0 for CYDMX064A16 and CYDMX064B16.
2. IRR1 and IRR2 not available for CYDMX256A16 and CYDMX256B16.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-08090 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 2, 2011
[+] Feedback



No Preview Available !

CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Contents
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Description ..................................................... 4
Power Supply .............................................................. 4
ADM Interface Read or Write Operation ..................... 4
Standard SRAM Interface Read or Write Operation ... 5
Byte Select Operation ................................................. 5
Chip Select Operation ................................................. 5
Output Enable Operation ............................................. 5
Mailbox Interrupts ........................................................ 5
Arbitration Logic .......................................................... 5
Input Read Register .................................................... 5
Output Drive Register .................................................. 5
Architecture ...................................................................... 6
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
Electrical Characteristics for VCC = 1.8 V ...................... 8
Electrical Characteristics for VCC = 2.5 V .................... 10
Electrical Characteristics for 3.0 V ............................... 11
Capacitance .................................................................... 11
Switching Characteristics for VCC = 1.8 V ................... 12
Switching Waveforms .................................................... 15
Ordering Information ...................................................... 21
Ordering Code Definitions ......................................... 21
Package Diagram ............................................................ 22
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC Solutions ......................................................... 25
Document #: 001-08090 Rev. *G
Page 2 of 25
[+] Feedback



No Preview Available !

CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Pin Configurations
1
A A5
Figure 1. 100-ball 0.5 mm pitch BGA (Top View)
2 3 4 5 6 7 8 9 10
A8 A11 UB#R VSS ADV#R I/OR15 I/OR12 I/OR10 VSS A
B A3 A4 A7 A9 CE#R WE#R OE#R VDDIOR I/OR9 I/OR6 B
C A0 A1 A2 A6 LB#R IRR1[3] I/OR14 I/OR11 I/OR7 VSS C
D ODR4 ODR2 BUSY#R INT#R A10 A12[4] I/OR13 I/OR8 I/OR5 I/O2R D
E VSS DNU ODR3 INT#L VSS VSS I/OR4 VDDIOR I/OR1 VSS E
F SFEN# ODR1 BUSY#L DNU VCC VSS I/OR3 I/OR0 I/OL15 VDDIOL F
G ODR0 DNU DNU DNU OE#L I/OL3 I/OL11 I/OL12 I/OL14 I/OL13 G
H DNU DNU DNU LB#L CE#L I/OL1 VDDIOL MSEL DNU I/OL10 H
J DNU DNU DNU IRR0[5] VCC VSS I/OL4 I/OL6 I/OL8 I/OL9 J
K DNU DNU DNU UB#L ADV#L WE#L I/OL0 I/OL2 I/OL5 I/OL7 K
1 2 3 4 5 6 7 8 9 10
.
Notes
3. This pin is A13 for CYDMX256A16 and CYDMX256B16.
4. This pin is DNU for CYDMX064A16 and CYDMX064B16.
5. This pin is DNU for CYDMX256A16 and CYDMX256B16.
6. DNU pins are “do not use” pins. No trace or power component can be connected to these pins.
Document #: 001-08090 Rev. *G
Page 3 of 25
[+] Feedback



No Preview Available !

CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Pin Definitions
Left Port
Right Port
CS#L
CS#R
WE#L
WE#R
OE#L
OE#R
A0–A13
MSEL
IOL0–IOL15
IOR0–IOR15
ADV#L
ADV#R
UB#L
UB#R
LB#L
LB#R
INT#L
INT#R
BUSY#L
BUSY#R
SFEN#
IRR0-IRR1
ODR0-ODR4
VCC
GND
VDDIOL
VDDIOR
DNU
Description
Chip Select
Read/Write Enable
Output Enable
Address (A0–A11 for 4K device; A0–A12 for 8K device; A0–A13 for 16K device)
Right Port Interface Mode Select (0: Standard SRAM; 1: Address/Data Mux)
Address/Data Bus Input/Output
Address Latch Enable; ADV#R only use when R-port is in ADM mode
Upper Byte Select (IO8–IO15)
Lower Byte Select (IO0–IO7)
Interrupt Flag
Busy Flag
Special Function Enable Signal
Input Signals for Input Read Registers for CYDMX128A16, CYDMX128B16,
CYDMX064A16 and CYDMX064B16;
IRR0 is DNU and IRR1 is A13 for CYDMX256A16 and CYDMX256B16.
Output Signals for Output Drive Registers; These are open drained outputs.
Core Power Supply
Ground
Left Port IO Power Supply
Right Port IO Power Supply
No Connect; Do not connect trace or power component to these pins.
Functional Description
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 are low
power CMOS 16K/8K/4K × 16 dual-port static RAMs. The two
ports are: one dedicated time multiplexed address and data
(ADM) interface and one configurable standard SRAM or ADM
interface. The two ports permit independent, asynchronous read
and write access to any memory locations. Each port has
independent control pins: Chip Select (CS#), Write Enable
(WE#), and Output Enable (OE#). Two output flags are provided
on each port (BUSY# and INT#). BUSY# flag is triggered when
the port is trying to access the same memory location currently
being accessed by the other port. The Interrupt flag (INT#)
permits communication between ports or systems by means of
a mailbox. Power down feature is controlled independently on
each port by a Chip Select (CS#) pin.
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 are
available in 100-ball 0.5-mm pitch Ball Grid Array (BGA)
packages. Application areas include interprocessor and
multiprocessor designs, communications status buffering, and
dual-port video and graphics memory.
Power Supply
The core voltage (VCC) can be 1.8 V, 2.5 V, or 3.0 V, as long as
it is lower than or equal to the IO voltage. Each port operates on
independent IO voltages. This is determined by what is
connected to the VDDIOL and VDDIOR pins. The supported IO
standards are 1.8 V and 2.5 V LVCMOS and 3.0 V LVTTL.
ADM Interface Read or Write Operation
This description is applicable to both the left ADM port and right
port configured as an ADM port.
Three control signals, ADV#, WE#, and CS# are used to perform
the read and write operations. Address signals are first applied
to the IO bus along with CS# LOW. The addresses are loaded
from the IO bus in response to the rising edge of the Address
Latch Enable (ADV#) signal. It is necessary to meet the setup
(tAVDS) and hold (tAVDH) times given in the AC specifications with
valid address information to properly latch the addresses.
After the address signals are latched in, a read operation is
issued when WE# stays HIGH. The IO bus becomes High Z
when the address signals meet tAVDH. The read data is driven on
the IO bus tOE after the OE# is asserted LOW, and held until
tHZOE or tHZCS after the rising edge of OE# or CS#, whichever
comes first.
A write operation is issued when WE# is asserted LOW. The
write data is applied to the IO bus right after address meets the
hold time (tAVDH). And write data is written with the rising edge
of either WE# or CS#, whichever comes first, and meets data
setup (tSD) and hold (tHD) times.
Document #: 001-08090 Rev. *G
Page 4 of 25
[+] Feedback



CYDMX256B16 datasheet pdf
Download PDF
CYDMX256B16 pdf
View PDF for Mobile


Related : Start with CYDMX256B1 Part Numbers by
CYDMX256B16 16 K/8 K/4 K x 16 MoBL ADM 16 K/8 K/4 K x 16 MoBL ADM CYDMX256B16
Cypress Semiconductor
CYDMX256B16 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact