CY7C1426JV18 Datasheet PDF - Cypress Semiconductor

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CY7C1426JV18
Cypress Semiconductor

Part Number CY7C1426JV18
Description (CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
Page 28 Pages


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CY7C1411JV18, CwwYw7.DCat1aS4h2ee6t4JU.Vco1m8
CY7C1413JV18, CY7C1415JV18
36-Mbit QDR™-II SRAM 4-Word
Burst Architecture
Features
Separate independent read and write data ports
Supports concurrent transactions
300 MHz clock for high bandwidth
4-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 600 MHz) at 300 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR-II operates with 1.5 cycle read latency when DLL is
enabled
Operates similar to a QDR-I device with 1 cycle read latency
in DLL off mode
Available in x 8, x 9, x 18, and x 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1411JV18 – 4M x 8
CY7C1426JV18 – 4M x 9
CY7C1413JV18 – 2M x 18
CY7C1415JV18 – 1M x 36
Functional Description
The CY7C1411JV18, CY7C1426JV18, CY7C1413JV18, and
CY7C1415JV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports to access the memory array. The
read port has dedicated data outputs to support the read opera-
tions and the write port has dedicated data inputs to support the
write operations. QDR-II architecture has separate data inputs
and data outputs to completely eliminate the need to “turn
around” the data bus required with common IO devices. Access
to each port is through a common address bus. Addresses for
read and write addresses are latched on alternate rising edges
of the input (K) clock. Accesses to the QDR-II read and write
ports are completely independent of one another. To maximize
data throughput, read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C1411JV18), 9-bit words (CY7C1426JV18), 18-bit
words (CY7C1413JV18), or 36-bit words (CY7C1415JV18) that
burst sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K and C and C), memory bandwidth is
maximized while simplifying system design by eliminating bus
“turn arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on chip
synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
300 MHz
300
x8 965
x9 970
x18 1010
x36 1130
250 MHz
250
745
760
790
870
200 MHz
200
620
620
655
715
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12557 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 25, 2008
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Logic Block Diagram (CY7C1411JV18)
CY7C1411JV18, CY7C1426JV18
CY7C1413JV18, wCwYw7.DCata1S4he1e5t4UJ.cVo1m8
D[7:0]
8
A(19:0) 20
Address
Register
K
K
DOFF
VREF
WPS
NWS[1:0]
CLK
Gen.
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
20 A(20:0)
Read Data Reg.
32
16
16
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 8
8
8
8
8
CQ
CQ
Q[7:0]
Logic Block Diagram (CY7C1426JV18)
D[8:0]
9
A(19:0) 20
K
K
DOFF
VREF
WPS
BWS[0]
Address
Register
CLK
Gen.
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
20 A(19:0)
Read Data Reg.
36
18
18
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 9
9
9
9
9
CQ
CQ
Q[8:0]
Document Number: 001-12557 Rev. *C
Page 2 of 28
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Logic Block Diagram (CY7C1413JV18)
CY7C1411JV18, CY7C1426JV18
CY7C1413JV18, wCwYw7.DCata1S4he1e5t4UJ.cVo1m8
D[17:0]
18
A(18:0) 19
Address
Register
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
19 A(18:0)
Read Data Reg.
72
36
36
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 18
18
18
18
18
CQ
CQ
Q[17:0]
Logic Block Diagram (CY7C1415JV18)
D[35:0]
36
A(17:0) 18
Address
Register
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
18 A(17:0)
Read Data Reg.
144
72
72
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 36
36
36
36
36
CQ
CQ
Q[35:0]
Document Number: 001-12557 Rev. *C
Page 3 of 28
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CY7C1411JV18, CY7C1426JV18
CY7C1413JV18, wCwYw7.DCata1S4he1e5t4UJ.cVo1m8
Pin Configuration
The pin configuration for CY7C1411JV18, CY7C1413JV18, and CY7C1415JV18 follows. [1]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1411JV18 (4M x 8)
12345678
A
CQ NC/72M
A
WPS NWS1
K NC/144M RPS
B
NC NC NC
A NC/288M K
NWS0
A
C NC NC NC VSS A NC A VSS
D
NC
D4
NC
VSS
VSS
VSS
VSS
VSS
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
N NC D7 NC VSS A A A VSS
P NC NC Q7 A A C A A
R
TDO
TCK
A
A
A
C
A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D2
NC
NC
VREF
Q1
NC
NC
NC
NC
NC
TMS
CY7C1426JV18 (4M x 9)
1 2 3 4 5 6 7 8 9 10
A
CQ NC/72M
A
WPS
NC
K NC/144M RPS
A
A
B
NC NC NC
A NC/288M K
BWS0
A
NC NC
C NC NC NC VSS A NC A VSS NC NC
D
NC
D5
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS VDDQ NC
D3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q2
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS VDDQ NC
NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
N NC D8 NC VSS A A A VSS NC NC
P NC NC Q8 A A C A A NC D0
R
TDO
TCK
A
A
A
C
A
A
A TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-12557 Rev. *C
Page 4 of 28
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CY7C1426JV18 (CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture CY7C1426JV18
Cypress Semiconductor
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