22 sOE# I, PD
4 PE/HD I, PU
24, 23, 26, nF[1:0]
25, 1, 32, 3,
31 FS I
19, 20, 15,
16, 10, 11,
12 VDDQ3 PWR
5 VDDQ4 PWR
LVTTL/LVCMOS Reference Clock Input.
When MID or HIGH, Disables Phase-locked Loop (PLL) (except for condi-
tions of note 3). REF goes to outputs of Bank 1 and Bank 2. REF goes to
outputs of Bank 3 and Bank 4 through output dividers K and M. Set LOW for
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0
and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level
and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual
banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
Selects Positive or Negative Edge Control and High or Low output drive
strength. When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock, respectively. When at MID level,
the output drive strength is increased and the outputs synchronize with the
positive edge of the reference clock (see Table 6).
Three-level Select frequency and phase of the outputs (see Tables 1, 2, 3, 4, and 5).
Three-level Selects VCO operating frequency range (see Table 4).
Four banks of two outputs (see Tables 1, 2, and 3).
Power supply for Bank 1 and Bank 2 output buffers (see Table 7 for supply
Power supply for Bank 3 output buffers (see Table 7 for supply level
Power supply for Bank 4 output buffers (see Table 7 for supply level
Power supply for internal circuitry (see Table 7 for supply level constraints).
The outputs of the CY7B9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 1 and Table 2, respectively.
The three-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B9950 PLL operating frequency range that
corresponds to each FS level is given in Table 3.
Table 3. Frequency Range Select
Table 1. Output Divider Settings — Bank 3
K — Bank3 Output Divider
Table 2. Output Divider Settings — Bank 4
M — Bank4 Output Divider
FS PLL Frequency Range
L 24 to 50 MHz
M 48 to 100 MHz
H 96 to 200 MHz
Selectable output skew is in discrete increments of time unit
(tU).The value of tU is determined by the FS setting and the
maximum nominal frequency. The equation to be used to
determine the tU value is as follows: tU = 1 / (fNOM x MF)
where MF is a multiplication factor, which is determined by the
FS setting as indicated in Table 4.
1. “PD” indicates an internal pull-down and “PU” indicates an internal pull-up. “3” indicates a three-level input buffer
2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4. These states are used to program the phase of the respective banks (see Table 5).
Document #: 38-07338 Rev. *B
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