CY7B9950 Datasheet PDF - Cypress Semiconductor

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CY7B9950
Cypress Semiconductor

Part Number CY7B9950
Description High-Speed Multi-Phase PLL Clock Buffer
Page 9 Pages


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RoboClock
CY7B9950
2.5/3.3V, 200-MHz High-Speed Multi-Phase
PLL Clock Buffer
Features
• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• Output-output skew < 100 ps
• Cycle-cycle jitter < 100 ps
• ± 2% max output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
Eight LVTTL outputs driving 50terminated lines
LVCMOS/LVTTL over-voltage-tolerant reference input
Phase adjustments in 625-/1250-ps steps up to +7.5 ns
2x, 4x multiply and (1/2)x, (1/4)x divide ratios
Spread-Spectrum-compatible
Industrial temp. range: 40°C to +85°C
32-pin TQFP package
Description
The CY7B9950 RoboClockis a low-voltage, low-power,
eight-output, 200-MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance computer and communication systems.
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature allows the user to
skew the outputs to lead or lag the reference clock. Any one
of the outputs can be connected to feedback input to achieve
different reference frequency multiplication and divide ratios
and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin
controls the synchronization of the output signals to either the
rising or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA(3.3V).
Block Diagram
Pin Configuration
TEST PE/HD FS VDDQ1
REF
FB
1F1:0
2F1:0
3F1:0
4F1:0
33
PLL
3
3 Phase
3 Select
3 Phase
3 Select
3 Phase
Select
3 and /K
3 Phase
Select
3 and /M
1Q0
1Q1
2Q0
2Q1
3F1
4F0
4F1
PE/HD
VDDQ4
4Q1
4Q0
VSS
1
2
3
4
5
6
7
8
CY7B9950
24 1F1
23 1F0
22 sOE#
21 VDDQ1
20 1Q0
19 1Q1
18 VSS
17 VSS
3Q0
3Q1
VDDQ3
4Q0
4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07338 Rev. *B
Revised March 4, 2003



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RoboClock
CY7B9950
Pin Description
Pin
29
13
27
Name
REF
FB
TEST
I/O[1]
I
I
I
22 sOE# I, PD
4 PE/HD I, PU
24, 23, 26, nF[1:0]
25, 1, 32, 3,
2
I
31 FS I
19, 20, 15,
16, 10, 11,
6, 7
21
nQ[1:0]
VDDQ1[2]
O
PWR
12 VDDQ3[2] PWR
5 VDDQ4[2] PWR
14,30
8,9,17,18,
28
VDD[2]
VSS
PWR
PWR
Type
Description
LVTTL/LVCMOS Reference Clock Input.
LVTTL
Feedback Input.
Three-level
When MID or HIGH, Disables Phase-locked Loop (PLL) (except for condi-
tions of note 3). REF goes to outputs of Bank 1 and Bank 2. REF goes to
outputs of Bank 3 and Bank 4 through output dividers K and M. Set LOW for
normal operation.
Two-level
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0
and 2Q1) in a LOW state (for PE = H or M) 2Q0 and 2Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level
and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual
banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
Three-level
Selects Positive or Negative Edge Control and High or Low output drive
strength. When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock, respectively. When at MID level,
the output drive strength is increased and the outputs synchronize with the
positive edge of the reference clock (see Table 6).
Three-level Select frequency and phase of the outputs (see Tables 1, 2, 3, 4, and 5).
Three-level Selects VCO operating frequency range (see Table 4).
LVTTL
Four banks of two outputs (see Tables 1, 2, and 3).
Power
Power
Power
Power
Power
Power supply for Bank 1 and Bank 2 output buffers (see Table 7 for supply
level constraints).
Power supply for Bank 3 output buffers (see Table 7 for supply level
constraints).
Power supply for Bank 4 output buffers (see Table 7 for supply level
constraints).
Power supply for internal circuitry (see Table 7 for supply level constraints).
Ground.
Device Configuration
The outputs of the CY7B9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 1 and Table 2, respectively.
The three-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B9950 PLL operating frequency range that
corresponds to each FS level is given in Table 3.
Table 3. Frequency Range Select
Table 1. Output Divider Settings Bank 3
3F[1:0]
LL
HH
Other[4]
K Bank3 Output Divider
2
4
1
Table 2. Output Divider Settings Bank 4
4F[1:0]
LL
Other[4]
M Bank4 Output Divider
2
1
FS PLL Frequency Range
L 24 to 50 MHz
M 48 to 100 MHz
H 96 to 200 MHz
Selectable output skew is in discrete increments of time unit
(tU).The value of tU is determined by the FS setting and the
maximum nominal frequency. The equation to be used to
determine the tU value is as follows: tU = 1 / (fNOM x MF)
where MF is a multiplication factor, which is determined by the
FS setting as indicated in Table 4.
Notes:
1. PDindicates an internal pull-down and PUindicates an internal pull-up. 3indicates a three-level input buffer
2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4. These states are used to program the phase of the respective banks (see Table 5).
Document #: 38-07338 Rev. *B
Page 2 of 9



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RoboClock
CY7B9950
Table 4. MF Calculation
FS MF fNOM at which tU is 1.0 ns(MHz)
L 32
31.25
M 16
62.5
H8
125
Table 5. Output Skew Settings
nF[1:0]
LL[5]
LM
LH
ML
MM
MH
HL
HM
HH
Skew (1Q[0:1],2Q[0:1])
4tU
3tU
2tU
1tU
Zero Skew
+1tU
+2tU
+3tU
+4tU
In addition to determining whether the outputs synchronize to
the rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as
indicated in Table 6.
The CY7B9950 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain
both 3.3V and 2.5V output signals from one device. The core
power supply (VDD) must be set a level that is equal or higher
than on any one of the output power supplies.
Table 6. PE/HD Settings
PE/HD
L
M
H
Synchronization
Negative
Positive
Positive
Output Drive Strength[7]
Low Drive
High Drive
Low Drive
Skew (3Q[0:1])
Divide By 2
6tU
4tU
2tU
Zero Skew
+2tU
+4tU
+6tU
Divide By 4
Skew (4Q[0:1])
Divide By 2
v6tU
4tU
v2tU
Zero Skew
+2tU
+4tU
+6tU
Inverted[6]
Table 7. Power Supply Constraints
VDD
VDDQ1[8]
3.3V 3.3V or 2.5V
VDDQ3[8]
3.3V or 2.5V
2.5V
2.5V
2.5V
VDDQ4[8]
3.3V or 2.5V
2.5V
Governing Agencies
The following agencies provide specifications that apply to the
CY7B9950. The agency name and relevant specification is
listed below.
Table 8.
Agency Name
Specification
JEDEC
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
IEEE
1596.3 (Jitter Specs)
UL-194_V0 94 (Moisture Grading)
MIL 883E Method 1012.1 (Therma Theta JC)
Notes:
5. LL disables outputs if TEST = MID and sOE# = HIGH.
6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW.
7. Please refer to DC Parameterssection for IOH/IOL specifications.
8. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V
and VDDQ4 = 2.5V.
Document #: 38-07338 Rev. *B
Page 3 of 9



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RoboClock
CY7B9950
Absolute Maximum Conditions
Parameter
Description
VDD
VDD
VIN(MIN)
VIN(MAX)
TS
TA
TJ
ØJC
ØJA
ESDHBM
UL-94
Operating Voltage
Operating Voltage
Input Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Flammability Rating
MSL
Moisture Sensitivity Level
FIT Failure in Time
Condition
Functional @ 2.5V ± 5%
Functional @ 3.3V ± 10%
Relative to VSS
Relative to VDD
Non-functional
Functional
Functional
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
MIL-STD-883, Method 3015
@1/8 in.
Manufacturing Testing
Min.
Max.
2.375
2.625
2.97 3.63
VSS 0.3
65
VDD + 0.3
+150
40 +85
155
42
105
2000
V0
1
10
Unit
V
V
V
V
°C
°C
°C
°C/W
°C/W
V
ppm
DC Electrical Specifications @ 2.5V
Parameter
Description
Conditions
Min.
Max. Unit
VDD
VIL
VIH
VIHH[9]
VIMM[9]
VILL[9]
IIL
I3
IPU
IPD
VOL
VOH
IDDQ
2.5 Operating Voltage
2.5V ± 5%
2.375
2.625
V
Input LOW Voltage
REF, FB and sOE# Inputs
0.7 V
Input HIGH Voltage
1.7 V
Input HIGH Voltage
Input MID Voltage
Input LOW Voltage
3-Level Inputs
VDD 0.4
(TEST, FS, nF[1:0], PE/HD) (These pins are normally
wired to VDD,GND or unconnected.)
VDD/2 0.2
VDD/2 + 0.2
0.4
V
V
V
Input Leakage Current
3-Level Input DC Current
Input Pull-up Current
Input Pull-down Current
Output LOW Voltage
Output HIGH Voltage
Quiescent Supply Current
VIN = VDD/GND,VDD = max. (REF and FB inputs)
HIGH, VIN = VDD
MID, VIN = VDD/2
LOW, VIN = VSS
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV, PE/HD)
VIN = VSS, VDD = max.
VIN = VDD, VDD = max., (sOE#)
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
IOL = 20 mA (PE/HD = MID),(nQ[0:1])
IOH = 12 mA (PE/HD = L/H),(nQ[0:1])
IOH = 20 mA (PE/HD = MID),(nQ[0:1])
VDD = max., TEST = MID, REF = LOW, sOE# = LOW,
outputs not loaded
5
50
200
25
2.0
2.0
5 µA
200 µA
50 µA
µA
µA
100 µA
0.4 V
0.4 V
V
V
2 mA
IDD Dynamic Supply Current @ 100 MHz
CIN Input Pin Capacitance
Note:
9. These inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
150
4
mA
pF
Document #: 38-07338 Rev. *B
Page 4 of 9



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