CY62177DV20 Datasheet PDF - Cypress Semiconductor

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CY62177DV20
Cypress Semiconductor

Part Number CY62177DV20
Description 32-Mbit (2M x 16) Static RAM
Page 11 Pages


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CY62177DV20 MoBL2™
32-Mbit (2M x 16) Static RAM
Features
Very high speed: 70 ns
Wide voltage range: 1.7V – 2.2V
Ultra low active power
Typical active current: 2 mA at f = 1 MHz
Typical active current: 12 mA at f = fMAX
Ultra low standby power
Easy memory expansion with CE1, CE2, and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in 48-ball VFBGA package
Functional Description
The CY62177DV20 is a high performance CMOS static RAM
organized as 2M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life(MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
by 99% when addresses are not toggling. The device can also
be put into standby mode when deselected (CE1 HIGH or CE2
LOW or both BHE and BLE are HIGH). The input and output pins
(IO0 through IO15) are placed in a high impedance state when:
the device is deselected (CE1HIGH or CE2 LOW); outputs are
disabled (OE HIGH); both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH); when a write operation
is in progress (CE1 LOW, CE2 HIGH and WE LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO0 through IO7) is written
into the location specified on the address pins (A0 through A20).
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the address
pins (A0 through A20).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO8 to IO15. See the Truth Table on page 9
for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
2M × 16
RAM ARRAY
IO0–IO7
IO8–IO15
COLUMN DECODER
Power Down
Circuit
CE2
CE1
BHE
BLE
BHE
WE
OE
BLE
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocatuamSheenett4#U:.0ne0t1-44018 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 08, 2008
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Pin Configuration
CY62177DV20 MoBL2™
Figure 1. 48-Ball VFBGA (8 x 9.5 x 1.2 mm) Top View [1]
12 34 56
BLE OE A0 A1 A2 CE2
IO8 BHE A3 A4 CE1 IO 0
IO 9 IO 10 A5 A6 IO 1 IO 2
VSS IO11 A17 A7
IO3 Vcc
VCC IO 12 DNU A16 IO 4 Vss
IO 14 IO 13 A14 A15 IO 5 IO 6
IO 15 A19 A12 A13 WE IO 7
A18 A8 A9 A10 A11 A20
A
B
C
D
E
F
G
H
Product Portfolio
Product
CY62177DV20LL
VCC Range (V)
Min Typ[2] Max
1.7 1.8 2.2
Speed
(ns)
70
Power Dissipation
Operating ICC (mA)
f = 1 MHz
Typ[2]
Max
f = fmax
Typ[2]
Max
Standby ISB2 (μA)
Typ[2]
Max
2 4 12 25 5 50
Notes
1. DNU pins must be connected to VSS or left open.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 001-44018 Rev. **
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CY62177DV20 MoBL2™
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Supply Voltage to Ground
Potential ......................................... –0.2V to VCC(max) + 0.2V
DC Voltage Applied to Outputs
in High Z State[3, 4].......................... –0.2V to VCC(max) + 0.2V
Electrical Characteristics
Over the Operating Range
DC Input Voltage[3, 4] ....................... –0.2V toVCC(max) + 0.2V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA
Operating Range
Device
Range
Ambient
Temperature
VCC[5]
CY62177DV20LL Industrial –40°C to +85°C 1.7V to 2.2V
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
IOH = –0.1 mA
VOL
Output LOW Voltage
IOL = 0.1 mA
VIH Input HIGH Voltage VCC = 1.7V to 2.2V
VIL Input LOW Voltage VCC = 1.7V to 2.2V
IIX
Input Leakage Current
GND < VI < VCC
IOZ Output Leakage Current GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
f = fmax = 1/tRC
VCC = VCC(max)
Current
f = 1 MHz
IOUT = 0 mA
CMOS levels
ISB1 Automatic CE Power Down CE1 > VCC – 0.2V or CE2 < 0.2V
Current – CMOS Inputs
VIN > VCC – 0.2V, VIN < 0.2V)
f = fmax(Address and Data Only),
f = 0 (OE, WE, BHE and BLE), VCC = VCC(max)
ISB2 Automatic CE Power Down CE1 > VCC – 0.2V or CE2 < 0.2V,
Current – CMOS Inputs
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max)
70 ns
Min Typ[2] Max
Unit
1.4 V
0.2 V
1.4
–0.2
VCC + 0.2V V
0.4 V
–1 +1 μA
–1 +1 μA
12 25 mA
2 4 mA
5 100 μA
5 50 μA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
COUT
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
Max Unit
12 pF
12 pF
Notes
3. VIL(min) = –2.0V for pulse durations less than 20 ns.
4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
5. Full Device AC operation is based on a 100 μs ramp time from 0 to VCC(min) and 100 μs wait time after VCC stabilization.
Document #: 001-44018 Rev. **
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CY62177DV20 MoBL2™
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
ΘJA Thermal Resistance
(Junction to Ambient)
ΘJC Thermal Resistance
(Junction to Case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveforms
VFBGA
55
16
Unit
°C/W
°C/W
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
VCC(typ)
10%
90%
90%
10%
R2 GND
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
RTH
V
Parameters
R1
R2
RTH
VTH
1.8V
13500
10800
6000
0.80
Unit
Ω
Ω
Ω
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
VDR
ICCDR
tCDR[6]
tR[7]
VCC for Data Retention
Data Retention Current
VCC = 1.0V, CE1 > VCC – 0.2V, CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Chip Deselect to Data
Retention Time
Operation Recovery Time
Min Typ[2] Max
1.0
25
Unit
V
μA
0 ns
tRC ns
Data Retention Waveform
VCC
CE1 or
BHE.BLE [8]
or
CE2
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.0 V
VCC(min)
tR
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
8. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 001-44018 Rev. **
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