CLA4603-085LF Datasheet PDF - Skyworks Solutions

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CLA4603-085LF
Skyworks Solutions

Part Number CLA4603-085LF
Description Surface Mount Limiter Diode
Page 8 Pages


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DATA SHEET
CLA4603-085LF: Surface Mount Limiter Diode
Applications
Low loss, high power limiters
Receiver protectors
Features
Low thermal resistance: 96 °C/W
Typical threshold level: +9 dBm
Low capacitance: 0.33 pF
Low profile, ultra-miniature QFN (3-pin, 2 x 2 mm) package
(MSL1, 260 °C per JEDEC J-STD-020)
Figure 1. CLA4603-085LF Block Diagram
Description
The CLA4603-085LF is a surface mountable, low capacitance
silicon PIN limiter diode designed as a shunt connected PIN diode
for high power limiter applications from 10 MHz to over 6 GHz.
Maximum resistance at 10 mA is 2 Ω and maximum capacitance
at 6 V is 0.4 pF. The combination of low junction capacitance, low
parasitic inductance, low thermal resistance, and nominal 1.5 μm
I-region width, makes the CLA4603-085LF useful in large signal
limiter applications. The threshold level is +9 dBm, nominal.
A block diagram of the CLA4603-085LF is shown in Figure 1. The
absolute maximum ratings of the CLA4603-085LF are provided in
Table 1. Electrical specifications are provided in Table 2.
Typical performance characteristics of the CLA4603-085LF are
provided in Table 3 and illustrated in Figure 4.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201637F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • June 13, 2013
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DATA SHEET • CLA4603-085LF SURFACE MOUNT LIMITER DIODE
Table 1. CLA4603-085LF Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Reverse voltage
VR 45 V
Forward current @ 25 °C
IF
1.5 A
CW power dissipation @ 85 °C
PD
1W
Peak pulse power dissipation@ 85 °C (10% duty cycle)
10 W
Storage temperature
TSTG
65 +200
°C
Junction temperature
TJ
175 °C
Operating temperature
TA
40 +150
°C
Electrostatic Discharge:
Charged Device Model (CDM), Class 4
Human Body Model (HMB), Class 1C
Machine Model (MM), Class A
ESD
1000 V
1000 V
150 V
Note: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other
parameters set at or below their nominal value. Exceeding any of the limits listed here may result in permanent damage to the device.
CAUTION: Although this device is designed to be as robust as possible, Electrostatic Discharge (ESD) can damage this device. This device
must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body
or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times.
Table 2. CLA4603-085LF Electrical Specifications (Note 1)
(TA = +25 °C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Breakdown voltage
VB IR = 10 μA
Reverse current
IR VR = 16 V
Capacitance
CT f = 1 MHz, VR = 6 V
Series resistance
RS f = 500 MHz, IF = 10 mA
Series inductance
LS
Carrier lifetime
TL IF = 10 mA
I region width
W
CW thermal resistance
θJC Junction-to-case
Peak thermal resistance
θP Single 1 μs pulse width,
junction-to-case (10%
duty cycle)
Note 1: Performance is guaranteed only under the conditions listed in this Table.
Min
20
Typical
0.33
1.7
0.3
10
1.5
96
9.6
Max
45
1
0.40
2.0
Units
V
μA
pF
Ω
nH
ns
μm
°C/W
°C/W
Table 3. Typical Performance @ 25 °C
Part Number
Insertion Loss
@ –10 dBm
(dB)
Input Power for
1 dB Loss
(dBm)
Maximum Pulsed
Input Power
(dBm)
Output @ Maximum
Pulsed Input
(dBm)
CLA4603-085LF
0.1
+9 +48
+22
Notes:
Limiter power results @ 1 GHz for shunt connected, single limiter diode and DC return in 50 Ω line.
Maximum pulsed power for 1 μs pulse and 0.1% duty factor with chip @ 25 °C heat sink. Derate linearly to 0 W @ 175 °C.
Maximum CW input power @ 25 °C heat sink. Derate linearly to 0 W @ 175 °C.
Recovery time to insertion loss from limiting state.
Maximum CW
Input power
(W)
3
Recovery Time
(ns)
10
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Functional Description
The PIN limiter diode can be described as an incident power
controlled, RF variable resistor. When there is no large input
signal present, the impedance of the limiter diode is at its
maximum, which produces minimum insertion loss, typically
less than 0.1 dB. The presence of a large input signal
temporarily forces the impedance of the diode to a much lower
value, which produces an impedance mismatch that reflects the
majority of the input signal power back towards its source.
During the limiting process, a DC current is generated by the PIN
limiter diode. The current is not the result of rectification, but is
the result of charge carriers being forced into the I layer by the
forward alternations of the large input signal. A complete path
must be provided for this current or the diode is not capable of
limiting. Therefore, an RF choke or similar structure must be
provided to complete the path for DC current flow.
DATA SHEET • CLA4603-085LF SURFACE MOUNT LIMITER DIODE
The DC block capacitors shown in Figure 2 are optional; they
protect the limiter diode from external DC voltage that may be
present in the source or load circuits.
A cross section of the suggested printed circuit board design is
shown in Figure 3. The via shown in this view is critical, both for
electrical performance and for thermal performance. It is
recommended that several vias should be placed under the
entire footprint of the exposed paddle (pin 2) to minimize both
electrical inductance to the system ground and thermal
resistance to the system heat sink.
For more information about the operation of limiter diodes, refer
to the Skyworks Application Note, PIN Limiter Diodes in Receiver
Protectors, document number 200480.
Figure 2. Single Stage Limiter Circuit
Figure 3. Cross-Sectional View of Suggested Printed Circuit Board
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201637F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • June 13, 2013
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DATA SHEET • CLA4603-085LF SURFACE MOUNT LIMITER DIODE
Typical Performance Characteristics
(TA = 25 °C, Unless Otherwise Noted)
Figure 4. Output Power and Insertion Loss vs Input Power
(f = 2.5 GHz, Board Loss Included)
High Power Limiter Design Application
The CLA4603-085LF PIN limiter diode is designed for shunt
applications in receiver protection power limiter circuits.
Compared to other surface mount packages, the design of the
QFN package produces lower thermal resistance and also reduces
the effects of the parasitic inductance of the anode bond wires.
A cross-sectional view of the CLA4603-085LF PIN limiter diode is
shown in Figure 5. The cathode of the die is soldered directly to
the top of the exposed paddle. This paddle is composed of copper,
so its thermal resistance is very low.
The copper ground paddle minimizes the total thermal resistance
between the I layer, which is the location where most heat is
generated under normal operation, and the surface to which the
package is mounted. Minimal thermal resistance between the I
layer and the external environment minimizes junction
temperature.
The electrically equivalent circuit of the CLA4603-085LF PIN
limiter diode is shown in Figure 6. The inductances of pins 1 and
2, as well as the inductances of the bond wires are in series with
the input and output transmission lines of the external circuit
rather than the portion of the circuit that contains the shunt PIN
limiter diode.
Figure 5. Cross-Sectional View of the CLA4603-085LF
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
4 June 13, 2013 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201637F
Free Datasheet http://www.datasheet4u.net/



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