CAT25C33 Datasheet PDF - Catalyst Semiconductor

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CAT25C33
Catalyst Semiconductor

Part Number CAT25C33
Description (CAT25C33 / CAT25C65) 32K/64K-Bit SPI Serial CMOS EEPROM
Page 11 Pages


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CAT25C33/65
32K/64K-Bit SPI Serial CMOS EEPROM
FEATURES
s 10 MHz SPI compatible
s 1,000,000 program/erase cycles
s 1.8 to 6.0 volt operation
s 100 year data tetention
s Hardware and software protection
s Low power CMOS technology
s SPI modes (0,0 &1,1)
s Commercial, industrial, automotive and extended
rtstemperature ranges
s Self-timed write cycle
s 8-pin DIP/SOIC and 14-pin TSSOP
s 64-byte page write buffer
s Block write protection
– Protect first page, last page, any 1/4 or lower
1/2 of EEPROM array
DESCRIPTION
aThe CAT25C33/65 is a 32K/64K-Bit SPI Serial CMOS
EEPROM internally organized as 4Kx8/8Kx8 bits.
Catalyst’s advanced CMOS Technology substantially
Preduces device power requirements. The CAT25C33/
65 features a 64-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
dthough a Chip Select (CS). In addition to the Chip Select,
the clock input (SCK), data in (SI) and data out (SO) are
required to access the device. The HOLD pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C32/64 is
designed with software and hardware write protection
features including Block write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and
20-pin TSSOP packages.
ePIN CONFIGURATION
www.DataSheet4U.com
SOIC Package (S, V, GV) TSSOP Package (U14, Y14)
BLOCK DIAGRAM
uCS
SO
tinWP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
DIP Package (P, L, GL)
CS 1
SO 2
NC 3
NC 4
NC 5
WP 6
VSS 7
14 VCC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
nCS
SO
WP
oVSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
cPIN FUNCTIONS
Pin Name
Function
isSO Serial Data Output
SCK
Serial Clock
DWP Write Protect
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
XDEC
E2PROM
ARRAY
DATA IN
STORAGE
HIGH VOLTAGE/
VCC +1.8V to +6.0V Power Supply
STATUS
TIMING CONTROL
VSS Ground
REGISTER
CS Chip Select
SI
HOLD
Serial Data Input
Suspends Serial Input
NC No Connect
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1000, Rev. H



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CAT25C33/65
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. 55°C to +125°C Stresses above those listed under Absolute Maximum
Storage Temperature ....................... 65°C to +150°C
Voltage on any Pin with
Respect to VSS1) ................... 2.0V to +VCC +2.0V
Ratingsmay cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
VCC with Respect to VSS ................................ 2.0V to +7.0V
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
mance and reliability.
rtsRELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND(3)
aTDR(3)
VZAP(3)
PILTH(3)(4)
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
1,000,000
100
2000
100
Typ.
Max.
Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
dVCC = +1.8V to +6.0V, unless otherwise specified.
eSymbol
uICC1
ICC2
tinISB(5)
ILI
nILO
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Min.
Limits
Typ.
Max.
10
2
1
2
3
oVIL(3)
VIH(3)
cVOL1
isVOH1
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.7
VCC - 0.8
VCC x 0.3
VCC + 0.5
0.4
VOL2
DVOH2
Output Low Voltage
Output High Voltage
VCC-0.2
0.2
Units
mA
mA
µA
µA
µA
V
V
V
V
V
V
Test Conditions
VCC = 5V @ 10MHz
SO=open; CS=Vss
VCC = 5.0V
FCLK = 10MHz
CS = VCC
VIN = VSS or VCC
VOUT = 0V to VCC,
CS = 0V
4.5VVCC<5.5V
IOL = 3.0mA
IOH = -1.6mA
1.8VVCC<2.7V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
(5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1000, Rev. H
2 © 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice



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CAT25C33/65
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
Test Conditions
Max.
Units Conditions
COUT Output Capacitance (SO)
8 pF VOUT=0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF VIN=0V
A.C. CHARACTERISTICS
rtsSYMBOL PARAMETER
Vcc=
1.8V-6.0V
Min. Max.
Limits
VCC =
2.5V-6.0V
Min. Max.
VCC =
4.5V-5.5V
Min. Max.
Test
UNITS Conditions
tSU Data Setup Time
50 50
20
ns
tH Data Hold Time
50 50
20
ns
atWH SCK High Time
250 125
40
ns
tWL SCK Low Time
250 125
40
ns
PfSCK
tLZ
dtRI(1)
etFI(1)
tHD
utCD
Clock Frequency
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
DC 1 DC
50
2
2
100 100
100 100
3 DC 10
50 50
22
22
40
40
MHz
ns
µs
µs
ns
ns
CL = 50pF
tWC Write Cycle Time
10 10
5 ms
tintV Output Valid from Clock Low
250
250
80 ns
tHO Output Hold Time
00
0
ns
tDIS Output Disable Time
250 250
75 ns
ntHZ HOLD to Output High Z
150 100
50 ns
otCS CS High Time
500 250
200
ns
tCSS CS Setup Time
500 250
100
ns
ctCSH CS Hold Time
500 250
100
ns
isNOTE:
D(1) This parameter is tested initially and after a design or process change that affects the parameter.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1000, Rev. H



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CAT25C33/65
FUNCTIONAL DESCRIPTION
PIN DESCRIPTION
The CAT25C33/65 supports the SPI bus data SI: Serial Input
transmission protocol. The synchronous Serial Peripheral SI is the serial data input pin. This pin is used to input all
Interface (SPI) helps the CAT25C33/65 to interface opcodes, byte addresses, and data to be written to the
directly with many of todays popular microcontrollers. 25C33/65. Input data is latched on the rising edge of the
The CAT25C33/65 contains an 8-bit instruction register. serial clock.
(The instruction set and the operation codes are detailed
in the instruction set table)
SO: Serial Output
SO is the serial data output pin. This pin is used to
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
transfer data out of the 25C33/65. During a read cycle,
data is shifted out on the falling edge of the serial clock.
rtsFigure 1. Sychronous Data Timing
VIH tCS
CS
PaSCK
dSI
VIL
tCSS
VIH
VIL
VIH
VIL
tWH
tSU tH
VALID IN
ueVOH
SO
VOL
HI-Z
tinNote: Dashed Line= mode (1, 1) — — — —
tCSH
tWL
tRI
tFI
tV
tHO
tDIS
HI-Z
INSTRUCTION SET
Instruction
nWREN
oWRDI
RDSR
cWRSR
isREAD
DWRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Power-Up Timing(2)(3)
Symbol
Parameter
Max.
Units
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1 ms
1 ms
Note:
(1) X=0 for 25010, 25020. X=A8 for 25040
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Doc. No. 1000, Rev. H
4 © 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice



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