CAT24C01 Datasheet PDF - Catalyst Semiconductor

www.Datasheet-PDF.com

CAT24C01
Catalyst Semiconductor

Part Number CAT24C01
Description (CAT24C01 - CAT24C16) Serial EPROM
Page 17 Pages


CAT24C01 datasheet pdf
Download PDF
CAT24C01 pdf
View PDF for Mobile

No Preview Available !

CAT24C01/02/04/08/16
1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
FEATURES
Supports Standard and Fast I2C Protocol
1.8 V to 5.5 V Supply Voltage Range
16-Byte Page Write Buffer
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant 8-lead PDIP, SOIC, MSOP
and TSSOP, 8-pad TDFN and 5-lead TSOT-23
packages.
For Ordering Information details, see page 16.
DEVICE DESCRIPTION
The CAT24C01/02/04/08/16 are 1-Kb, 2-Kb, 4-Kb,
8-Kb and 16-Kb respectively CMOS Serial EEPROM
devices organized internally as 8/16/32/64 and 128
pages respectively of 16 bytes each. All devices support
both the Standard (100 kHz) as well as Fast (400 kHz)
I2C protocol.
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile memory
in one internal write cycle. Data is read by providing a
starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address
up to eight CAT24C01 or CAT24C02, four CAT24C04,
two CAT24C08 and one CAT24C16 device on the
same bus.
PIN CONFIGURATION
PDIP (L)
SOIC (W)
TSSOP (Y)
MSOP (Z)
TDFN (VP2)
CAT24C16 / 08 / 04 / 02 / 01
NC / NC / NC / A0 / A0
NC / NC / A1 / A1 / A1
NC / A2 / A2 / A2 / A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
www.DataSheet4U.com
FUNCTIONAL SYMBOL
TSOT-23 (TD)
SCL 1
VSS 2
SDA 3
5 WP
4 VCC
SCL
A2, A1, A0
VCC
CAT24Cxx
SDA
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
A0, A1, A2
SDA
SCL
WP
VCC
VSS
NC
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
No Connect
WP
VSS
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1115, Rev. C



No Preview Available !

CAT24C01/02/04/08/16
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65°C to +150°C
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS(3)
Symbol
NEND(4)
TDR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Test Conditions
ICCR
ICCW
ISB
IL
Read Current
Write Current
Standby Current
I/O Pin Leakage
Read, fSCL = 400 kHz
Write, fSCL = 400 kHz
All I/O Pins at GND or VCC
Pin at GND or VCC
VIL
VIH
VOL1
VOL2
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
VCC 2.5 V, IOL = 3.0 mA
VCC < 2.5 V, IOL = 1.0 mA
Min Max
1
1
1
1
-0.5
VCC x 0.7
VCC x 0.3
VCC + 0.5
0.4
0.2
Units
mA
mA
μA
μA
V
V
V
V
PIN IMPEDANCE CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Conditions
Max Units
CIN(3) SDA I/O Pin Capacitance
VIN = 0 V
8 pF
CIN(3)
IWP(5)
Input Capacitance (other pins)
WP Input Current
VIN = 0 V
VIN < VIH, VCC = 5.5 V
6 pF
200
VIN < VIH, VCC = 3.3 V
VIN < VIH, VCC = 1.8 V
150
μA
100
VIN > VIH
1
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci-
fication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
Doc. No. 1115, Rev. C
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice



No Preview Available !

CAT24C01/02/04/08/16
A.C. CHARACTERISTICS(1)
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C.
Symbol
FSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF(2)
tSU:STO
tBUF
tAA
tDH
Ti(2)
tSU:WP
tHD:WP
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Standard
Min Max
100
4
4.7
4
4.7
0
250
1000
300
4
4.7
3.5
100
100
0
2.5
tWR
tPU(2, 3)
Write Cycle Time
Power-up to Ready Mode
5
1
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Fast
Min Max
400
0.6
1.3
0.6
0.6
0
100
300
300
0.6
1.3
0.9
100
100
0
2.5
5
1
Units
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
μs
ns
ns
μs
μs
ms
ms
A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x VCC to 0.8 x VCC
50 ns
0.3 x VCC, 0.7 x VCC
0.5 x VCC
Current Source: IOL = 3 mA (VCC 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1115, Rev. C



No Preview Available !

CAT24C01/02/04/08/16
POWER-ON RESET (POR)
Each CAT24Cxx* incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
A CAT24Cxx device will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
* For common features, the CAT24C01/02/04/08/16 will be refered
to as CAT24Cxx
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device ad-
dress when cascading multiple devices. When not driven,
these pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write opera-
tions, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24Cxx supports the Inter-Integrated Circuit (I2C)
Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by
a Master device, which generates the serial clock and
all START and STOP conditions. The CAT24Cxx acts
as a Slave device. Master and Slave alternate as either
transmitter or receiver.
I2C BUS PROTOCOL
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDA while SCL is HIGH. The START acts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. For normal Read/Write opera-
tions, the first 4 bits of the Slave address are fixed at
1010 (Ah). The next 3 bits are used as programmable
address bits when cascading multiple devices and/or as
internal address bits. The last bit of the slave address,
R/W, specifies whether a Read (1) or Write (0) operation
is to be performed. The 3 address space extension bits
are assigned as illustrated in Figure 2. A2, A1 and A0
must match the state of the external address pins, and
a10, a9 and a8 are internal address bits.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge the address byte and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9th clock cycle. As long as the Master acknowledges
the data, the Slave will continue transmitting. The Master
terminates the session by not acknowledging the last
data byte (NoACK) and by issuing a STOP condition.
Bus timing is illustrated in Figure 4.
Doc. No. 1115, Rev. C
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice



CAT24C01 datasheet pdf
Download PDF
CAT24C01 pdf
View PDF for Mobile


Related : Start with CAT24C0 Part Numbers by
CAT24C00 128-Bit Serial EEPROM CAT24C00
Catalyst Semiconductor
CAT24C00 pdf
CAT24C01 (CAT24C01 - CAT24C16) Serial EPROM CAT24C01
Catalyst Semiconductor
CAT24C01 pdf
CAT24C01 CMOS Serial EEPROM CAT24C01
ON Semiconductor
CAT24C01 pdf
CAT24C01B 1K-Bit Serial EEPROM CAT24C01B
Catalyst Semiconductor
CAT24C01B pdf
CAT24C02 (CAT24C01 - CAT24C16) Serial EPROM CAT24C02
Catalyst Semiconductor
CAT24C02 pdf
CAT24C02 CMOS Serial EEPROM CAT24C02
ON Semiconductor
CAT24C02 pdf
CAT24C021 Supervisory Circuits with I2C Serial CMOS E2PROM/ Precision Reset Controller and Watchdog Timer CAT24C021
Catalyst Semiconductor
CAT24C021 pdf
CAT24C022 Supervisory Circuits with I2C Serial CMOS E2PROM/ Precision Reset Controller and Watchdog Timer CAT24C022
Catalyst Semiconductor
CAT24C022 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact