C1251 Datasheet PDF - NEC

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C1251
NEC

Part Number C1251
Description UPC1251
Page 12 Pages


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DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG
www.datasheet4u.com SINGLE POWER SUPPLY DUAL OPERATIONAL AMPLIFIERS
<R> DESCRIPTION
The μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG are dual operational amplifiers which are designed to
operate for a single power supply. It includes features of low-voltage operation, a common-mode input voltage that
range from V(GND) level, an output from a V(GND) level that is determined by the output stage of class C push-
pull circuit and a 50 μA(TYP.) constant current, and a low current consumption.
In addition, this can operate at both positive and negative power supply and it can be extensively used in various
amplifier circuits.
The μ PC1251GR-9LG, μ PC1251MP-KAA which expands temperature type is suited for wide operating ambient
temperature use, and μ PC358GR-9LG is used for general purposes.
A DC parameter selection that is compatible to operational amplifiers is also available.
μ PC451GR-9LG, μ PC324GR-9LG which are quad types with the same circuit configuration are also available as
series of operational amplifiers.
<R> FEATURES
• Input Offset Voltage
±2 mV (TYP.)
• Internal frequency compensation
• Input Offset Current
±5 nA (TYP.)
• Output short-circuit protection
• Large Signal Voltage Gain 100000 (TYP.)
• Small Package
The mounting area is reduced to 40% or 66% compared to the conventional 8-pin plastic SOP as shown in the
following diagram.
Package
Subject part number
Outline comparison
Standard SOP
μ PC1251G2,
μ PC358G2
TSSOP
μ PC1251GR-9LG,
μ PC358GR-9LG
TSSOP (2.8 x 2.9)
μ PC1251MP-KAA
(Mounting area ratio)
6.5 4.4
6.4
5.2
(100%)
3.15
(60%)
2.8 4.0
2.9
(34%)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G17929EJ3V0DS00 (3rd edition)
Date Published December 2007 NS
2006, 2007
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.



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μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG
<R> ORDERING INFORMATION
Part Number
μ PC1251GR-9LG-E1-A Note
Selected Grade
Standard
μ PC1251GR-9LG-E2-A Note
www.datasheet4u.com
Standard
μ PC1251GR(5)-9LG-E1-A Note
DC
parameter selection
μ PC1251GR(5)-9LG-E2-A Note
DC
parameter selection
μ PC1251MP-KAA-E1-A Note
Standard
μ PC1251MP-KAA-E2-A Note
Standard
μ PC1251MP(5)-KAA-E1-A Note
DC
parameter selection
μ PC1251MP(5)-KAA-E2-A Note
DC
parameter selection
μ PC358GR-9LG-E1-A Note
Standard
μ PC358GR-9LG-E2-A Note
Standard
μ PC358GR(5)-9LG-E1-A Note
μ PC358GR(5)-9LG-E2-A Note
DC
parameter selection
DC
parameter selection
Package
8-pin plastic TSSOP (5.72 mm(225))
8-pin plastic TSSOP (5.72 mm(225))
8-pin plastic TSSOP (5.72 mm(225))
8-pin plastic TSSOP (5.72 mm(225))
8-pin plastic TSSOP (2.8 x 2.9)
8-pin plastic TSSOP (2.8 x 2.9)
8-pin plastic TSSOP (2.8 x 2.9)
8-pin plastic TSSOP (2.8 x 2.9)
8-pin plastic TSSOP(5.72 mm(225))
8-pin plastic TSSOP(5.72 mm(225))
8-pin plastic TSSOP(5.72 mm(225))
8-pin plastic TSSOP(5.72 mm(225))
Package Type
12 mm wide embossed taping
Pin 1 on draw-out side
12 mm wide embossed taping
Pin 1 at take-up side
12 mm wide embossed taping
Pin 1 on draw-out side
12 mm wide embossed taping
Pin 1 at take-up side
12 mm wide embossed taping
Pin 1 on draw-out side
12 mm wide embossed taping
Pin 1 at take-up side
12 mm wide embossed taping
Pin 1 on draw-out side
12 mm wide embossed taping
Pin 1 at take-up side
12 mm wide embossed taping
Pin 1 on draw-out side
12 mm wide embossed taping
Pin 1 at take-up side
12 mm wide embossed taping
Pin 1 on draw-out side
12 mm wide embossed taping
Pin 1 at take-up side
Note Pb-free (This product does not contain Pb in the external electrode and other parts.)
2 Data Sheet G17929EJ3V0DS



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μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG
EQUIVALENT CIRCUIT (1/2 Circuit)
<R> PIN CONFIGURATION (Marking side)
+ Q2
www.datasheetI4I u.coQm1
IN
Q8
6 μA 6 μA
Q3
Q4
CC
100 μA
V+
Q5
Q6
Q7
RSC
OUT
Q11 Q13
Q10
Q12
Q9 50 μA
V
OUT1 1
II1 2
IN1 3
V4
1
−+
2
+−
8 V+
7 OUT2
6 II2
5 IN2
<R> ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter
Voltage between V+ and VNote1
Symbol
V+ V
μ PC1251GR-9LG,
μ PC1251GR(5)-9LG
μ PC1251MP-KAA,
μ PC1251MP(5)-KAA
0.3 to +32
μ PC358GR-9LG,
μ PC358GR(5)-9LG
Unit
V
Differential Input Voltage
Input Voltage Note2
Output applied Voltage Note3
Total Power Dissipation Note4
Output Short Circuit Duration Note5
VID
VI
VO
PT
tS
±32
V0.3 to V+ 32
V0.3 to V+ + 0.3
440
Indefinite
V
V
V
mW
s
Operating Ambient Temperature
TA
40 to +125
40 to +85
°C
Storage Temperature
Tstg
55 to +150
55 to +125
°C
Note1. Note that reverse connections of the power supply may damage ICs.
2. The input voltage is allowed to input without damage or destruction independent of the magnitude of V+. Either
input signal is not allowed to go negative by more than 0.3 V. In addition, the input voltage that operates
normally as an operational amplifier is within the Common Mode Input Voltage range of an electrical
characteristic.
3. A range where input voltage can be applied to an output pin externally with no deterioration or damage to the
feature (characteristic). The input voltage can be applied regardless of the electric supply voltage. This
specification which includes the transition state such as electric power ON/OFF must be kept.
4. This is the value of when the glass epoxy substrate (size: 100 mm x 100 mm, thickness: 1 mm, 15% of the
substrate area where only one side is copper foiled is filling wired) is mounted.
Note that restrictions will be made to the following conditions for each product, and the derating ratio
depending on the operating ambient temperature.
μ PC1251GR-9LG: Derate at 5.5 mW/°C when TA > 69°C.
(Junction ambient thermal resistance Rth(J-A) = 183°C/W)
μ PC1251MP-KAA: Derate at 4.8 mW/°C when TA > 58°C.
(Junction ambient thermal resistance Rth(J-A) = 208°C/W)
μ PC358GR-9LG: Derate at 5.5 mW/°C when TA > 44°C.
(Junction ambient thermal resistance Rth(J-A) = 183°C/W)
5. Short circuits from the output to V+ can cause destruction. Pay careful attention to the total power dissipation
not to exceed the absolute maximum ratings, Note 4.
Data Sheet G17929EJ3V0DS
3



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μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage (Split)
Power Supply Voltage (V= GND)
Symbol
V±
V+
MIN.
±1.5
+3
TYP.
MAX.
±15
+30
Unit
V
V
www<.Rda>taEshLeEetC4uT.cRoImCAL CHARACTERISTICS
μ PC1251GR-9LG, μ PC1251MP-KAA, μ PC358GR-9LG (TA = 25°C, V+ = +5 V, V= GND)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Input Offset Voltage
VIO RS = 0 Ω
±2 ±7
Input Offset Current
Input Bias Current Note1
IIO
IB
±5 ±50
14 250
Large Signal Voltage Gain
Circuit Current Note2
AV RL 2 kΩ
ICC RL = , IO = 0 A
25000
100000
0.7
1.2
Common Mode Rejection Ratio
CMR
65 70
Supply Voltage Rejection Ratio
Output Voltage Swing
Common Mode lnput Voltage Range
SVR
VO
VICM
RL = 2 kΩ (Connect to GND)
65 100
0 V+ 1.5
0 V+ 1.5
Output Source Current
Output Sink Current
IO SOURCE VIN (+) = +1 V, VIN () = 0 V
IO SINK1
VIN () = +1 V, VIN (+) = 0 V
IO SINK2
VIN () = +1 V, VIN (+) = 0 V, VO = 200 mV
20
10
12
40
20
50
Channel Separation
f = 1 to 20 kHz
120
Unit
mV
nA
nA
mA
dB
dB
V
V
mA
mA
μA
dB
μ PC1251GR(5)-9LG, μ PC1251MP(5)-KAA, μ PC358GR(5)-9LG (TA = 25°C, V+ = +5 V, V= GND)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX. Unit
Input Offset Voltage
Input Offset Current
Input Bias Current Note1
Large Signal Voltage Gain
Circuit Current Note2
Common Mode Rejection Ratio
VIO
IIO
IB
AV
ICC
CMR
RS = 0 Ω
RL 2 kΩ
RL = , IO = 0 A
50000
65
±2
±5
14
100000
0.7
70
±3
±50
60
0.9
mV
nA
nA
mA
dB
Supply Voltage Rejection Ratio
Output Voltage Swing
Common Mode lnput Voltage Range
Output Source Current
Output Sink Current
Channel Separation
SVR
VO RL = 2 kΩ (Connect to GND)
VICM
IO SOURCE VIN (+) = +1 V, VIN () = 0 V
IO SINK1
VIN () = +1 V, VIN (+) = 0 V
IO SINK2
VIN () = +1 V, VIN (+) = 0 V, VO = 200 mV
f = 1 to 20 kHz
65
0
0
30
15
30
100 dB
V+ 1.5
V
V+ 1.4
V
40 mA
20 mA
50 70 μA
120 dB
Notes1. The input bias current flows in the direction where the IC flows out because the first stage is configured with a
PNP transistor.
2. This is a current that flows in the internal circuit. This current will flow irrespective of the channel used.
4 Data Sheet G17929EJ3V0DS



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