BUK9MLL-55PLL Datasheet PDF - NXP

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BUK9MLL-55PLL
NXP

Part Number BUK9MLL-55PLL
Description Dual TrenchPLUS Logic Level FET
Page 16 Pages


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BUK9MLL-55PLL
www.DataSheet4U.com
Dual TrenchPLUS logic level FET
Rev. 01 — 14 May 2009
Product data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect power transistor in SO20. Device is
manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring
very low on-state resistance, integrated current sensing transistors and over temperature
protection diodes.
1.2 Features and benefits
„ Integrated current sensors
„ Integrated temperature sensors
1.3 Applications
„ Lamp switching
„ Motor drive systems
„ Power distribution
„ Solenoid drivers
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
Static characteristics, FET1 and FET2
RDSon
drain-source
on-state resistance
VGS = 5 V; ID = 5 A;
Tj = 25 °C; see Figure 16;
see Figure 17
ID/Isense ratio of drain current Tj = 25 °C; VGS = 5 V; see
to sense current
Figure 18
V(BR)DSS drain-source
Tj = 25 °C; VGS = 0 V;
breakdown voltage ID = 250 µA
Min Typ Max Unit
- 42.5 50 m
2430 2700 2970 A/A
55 - - V



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BUK9MLL-55PLL
Dual TrenchPLUS logic level FET
2. Pinning information
Table 2. Pinning information
Pin Symbol Description
1 G1 gate 1
2 IS1 current sense 1
3 D1 drain 1
4 A1 anode 1
5 C1 cathode 1
6 G2 gate 2
7 IS2 current sense 2
8 D2 drain 2
9 A2 anode 2
10 C2
cathode 2
11 D2
drain 2
12 KS2 Kelvin source 2
13 S2
source 2
14 S2
source 2
15 D2
drain 2
16 D1
drain 1
17 KS1 Kelvin source 1
18 S1
source 1
19 S1
source 1
20 D1
drain 1
Simplified outline
20 11
1 10
SOT163-1
(SO20)
3. Ordering information
Graphic symbol
D1 A1
D2 A2
FET1
FET2
G1 IS1 S1 KS1 C1 G2 IS2 S2 KS2 C2
003aaa745
Table 3. Ordering information
Type number
Package
Name
Description
BUK9MLL-55PLL SO20
plastic small outline package; 20 leads; body width 7.5 mm
Version
SOT163-1
BUK9MLL-55PLL_1
Product data sheet
Rev. 01 — 14 May 2009
© NXP B.V. 2009. All rights reserved.
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BUK9MLL-55PLL
Dual TrenchPLUS logic level FET
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Limiting values, FET1 and FET2
VDS
VDGR
VGS
ID
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
Visol(FET-TSD) FET to temperature
sense diode isolation
voltage
25 °C < Tj < 150 °C
RGS = 20 k; 25 °C < Tj < 150 °C
Tsp = 25 °C; VGS = 5 V; see Figure 2; see Figure 3;
Tsp = 100 °C; VGS = 5 V; see Figure 2;
Tsp = 25 °C; tp 10 µs; pulsed; see Figure 3
Tsp = 25 °C; see Figure 1
[1][2]
[1][2]
-
-
-15
-
-
-
-
-55
-55
-
Source-drain diode, FET1 and FET2
IS
source current
Tsp = 25 °C;
ISM peak source current tp 10 µs; pulsed; Tsp = 25 °C
Avalanche ruggedness, FET1 and FET2
EDS(AL)S
non-repetitive
ID = 5.9 A; Vsup 55 V; VGS = 5 V; Tj(init) = 25 °C;
drain-source avalanche unclamped; see Figure 4;
energy
[1][2] -
-
[3][4] -
[5]
Electrostatic discharge, FET1 and FET2
VESD
electrostatic discharge HBM; C = 100 pF; R = 1.5 k; pins 3, 16 and 20 to
voltage
pins 1, 2, 17, 18 and 19 shorted
HBM; C = 100 pF; R = 1.5 k; pins 8, 11 and 15 to
pins 6, 7, 12, 13 and 14 shorted
HBM; C = 100 pF; R = 1.5 k; all pins
-
-
-
[1] Single device conducting.
[2] Current is limited by chip power dissipation rating.
[3] Single-pulse avalanche rating limited by maximum junction temperature of 150 °C.
[4] Repetitive rating defined in avalanche rating figure.
[5] Refer to application note AN10273 for further information.
Max Unit
55 V
55 V
15 V
5.9 A
3.7 A
61.3 A
3.3 W
150 °C
150 °C
100 V
4.7 A
61.3 A
72 mJ
4 kV
4 kV
0.15 kV
BUK9MLL-55PLL_1
Product data sheet
Rev. 01 — 14 May 2009
© NXP B.V. 2009. All rights reserved.
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BUK9MLL-55PLL
Dual TrenchPLUS logic level FET
120
Pder
(%)
80
40
003aab388
8
ID
(A)
6
4
2
003aac541
0
0 50 100 150 200
Tsp (°C)
0
0 50 100 150 200
Tsp (°C)
Fig 1. Normalized total power dissipation as a
function of solder point temperature, FET1 and
FET2
Fig 2. Continuous drain current as a function of
solder point temperature, FET1 and FET2
102
ID
(A)
10
1
10-1
Limit R DS on = VDS / ID
DC
003aac404
tp = 10 ms
100 ms
1 ms
10 ms
100 ms
10-2
10-1
1
10 102
VDS (V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and
FET2
BUK9MLL-55PLL_1
Product data sheet
Rev. 01 — 14 May 2009
© NXP B.V. 2009. All rights reserved.
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