BUK9624-55A Datasheet PDF - NXP Semiconductors

www.Datasheet-PDF.com

BUK9624-55A
NXP Semiconductors

Part Number BUK9624-55A
Description N-channel TrenchMOS logic level FET
Page 13 Pages


BUK9624-55A datasheet pdf
Download PDF
BUK9624-55A pdf
View PDF for Mobile

No Preview Available !

BUK9624-55A
N-channel TrenchMOS logic level FET
Rev. 02 — 31 January 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
AEC Q101 compliant
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V and 24 V loads
Automotive and general purpose
power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Symbol
VDS
ID
Ptot
Quick reference data
Parameter
Conditions
drain-source
voltage
Tj 25 °C; Tj 175 °C
drain current
VGS = 5 V; Tmb = 25 °C;
see Figure 1; see Figure 3
total power
dissipation
Tmb = 25 °C; see Figure 2
Min Typ Max Unit
- - 55 V
- - 46 A
- - 105 W



No Preview Available !

NXP Semiconductors
BUK9624-55A
N-channel TrenchMOS logic level FET
Table 1. Quick reference data …continued
Symbol Parameter
Conditions
Static characteristics
RDSon
drain-source
on-state
resistance
VGS = 4.5 V; ID = 25 A;
Tj = 25 °C
VGS = 10 V; ID = 25 A;
Tj = 25 °C
VGS = 5 V; ID = 25 A;
Tj = 25 °C; see Figure 12;
see Figure 13
Avalanche ruggedness
EDS(AL)S
non-repetitive
drain-source
avalanche energy
ID = 46 A; Vsup 25 V;
RGS = 50 ; VGS = 5 V;
Tj(init) = 25 °C; unclamped
Min Typ Max Unit
- - 26 m
- 19 21.7 m
- 20 24 m
- - 76 mJ
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G gate
D drain
S source
D mounting base; connected to
drain
Simplified outline
mb
2
13
SOT404 (D2PAK)
3. Ordering information
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
BUK9624-55A
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
BUK9624-55A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 31 January 2011
© NXP B.V. 2011. All rights reserved.
2 of 13



No Preview Available !

NXP Semiconductors
BUK9624-55A
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
VDGR
VGS
ID
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Conditions
Tj 25 °C; Tj 175 °C
RGS = 20 k
Tmb = 25 °C; VGS = 5 V; see Figure 1;
see Figure 3
IDM peak drain current
Tmb = 100 °C; VGS = 5 V; see Figure 1
Tmb = 25 °C; pulsed; tp 10 µs;
see Figure 3
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
VGSM
peak gate-source voltage
Source-drain diode
Tmb = 25 °C; see Figure 2
pulsed; tp 50 µs
IS source current
ISM peak source current
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
Tmb = 25 °C
pulsed; tp 10 µs; Tmb = 25 °C
ID = 46 A; Vsup 25 V; RGS = 50 ;
VGS = 5 V; Tj(init) = 25 °C; unclamped
120
Ider
(%)
80
03aa24
120
Pder
(%)
80
Min Max Unit
- 55 V
- 55 V
-10 10 V
- 46 A
- 33 A
- 188 A
- 105 W
-55 175 °C
-55 175 °C
-15 15 V
- 46 A
- 188 A
- 76 mJ
03na19
40 40
0
0 50 100 150 200
Tmb (°C)
0
0 50 100 150 200
Tmb (°C)
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
BUK9624-55A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 31 January 2011
© NXP B.V. 2011. All rights reserved.
3 of 13



No Preview Available !

NXP Semiconductors
BUK9624-55A
N-channel TrenchMOS logic level FET
103
ID
(A)
102
Limit RDSon = VDS /ID
10 P
tp
δ=
T
tp
T
1
1
t
D.C.
10
03na08
VDS (V)
tp = 10 μs
100 μs
1 ms
10 ms
100 ms
102
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Rth(j-a)
Thermal characteristics
Parameter
thermal resistance from junction
to mounting base
thermal resistance from junction
to ambient
Conditions
vertical in still air; lead length
5 mm; see Figure 4
Min Typ Max Unit
- - 1.4 K/W
- 50 - K/W
10
Zth(j-mb)
(K/W)
03na07
1
δ = 0.5
101
0.2
0.1
0.05
0.02
single pulse
102
106
105
104
103
P
tp
δ=
T
102
tp
T
t
101
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9624-55A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 31 January 2011
© NXP B.V. 2011. All rights reserved.
4 of 13



BUK9624-55A datasheet pdf
Download PDF
BUK9624-55A pdf
View PDF for Mobile


Related : Start with BUK9624-55 Part Numbers by
BUK9624-55 TrenchMOS transistor Logic level FET BUK9624-55
NXP
BUK9624-55 pdf
BUK9624-55 TrenchMOS transistor Logic level FET BUK9624-55
NXP
BUK9624-55 pdf
BUK9624-55A N-channel TrenchMOS logic level FET BUK9624-55A
NXP Semiconductors
BUK9624-55A pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact