BUK954R2-55B Datasheet PDF - NXP Semiconductors

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BUK954R2-55B
NXP Semiconductors

Part Number BUK954R2-55B
Description TrenchMOS logic level FET
Page 15 Pages


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BUK95/964R2-55B
TrenchMOS™ logic level FET
Rev. 02 — 8 October 2002
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using
Philips High-Performance Automotive TrenchMOS™ technology.
Product availability:
BUK954R2-55B in SOT78 (TO-220AB)
BUK964R2-55B in SOT404 (D2-PAK).
1.2 Features
s Very low on-state resistance
s 175 °C rated
s Q101 compliant
s Logic level compatible.
1.3 Applications
s Automotive systems
s Motors, lamps and solenoids
s 12 V and 24 V loads
s General purpose power switching.
1.4 Quick reference data
s EDS(AL)S 1.2 J
s ID 75 A
s RDSon = 3.5 m(typ)
s Ptot 300 W.
2. Pinning information
Table 1: Pinning - SOT78 and SOT404 simplified outlines and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
[1]
mb
mb
3 source (s)
mb mounting base,
connected to
drain (d)
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 package.
Symbol
d
g
MBB076
s



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BUK95/964R2-55B
TrenchMOS™ logic level FET
3. Limiting values
Table 2: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
VDGR
VGS
ID
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
RGS = 20 k
Tmb = 25 °C; VGS = 5 V;
Figure 2 and 3
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
Source-drain diode
IDR reverse drain current (DC)
Tmb = 100 °C; VGS = 5 V; Figure 2
Tmb = 25 °C; pulsed; tp 10 µs;
Figure 3
Tmb = 25 °C; Figure 1
Tmb = 25 °C
IDRM
peak reverse drain current
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source avalanche
energy
Tmb = 25 °C; pulsed; tp 10 µs
unclamped inductive load; ID = 75 A;
VDS 55 V; VGS = 5 V; RGS = 50 ;
starting Tmb = 25 °C
[1] Current is limited by power dissipation chip rating
[2] Continuous current is limited by package
Min
-
-
-
[1] -
[2] -
[2] -
-
-
55
55
[1] -
[2] -
-
-
Max Unit
55 V
55 V
±15 V
191 A
75 A
75 A
765 A
300
+175
+175
W
°C
°C
191 A
75 A
765 A
1.2 J
9397 750 10277
Product data
Rev. 02 — 8 October 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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BUK95/964R2-55B
TrenchMOS™ logic level FET
120
Pder
(%)
80
03na19
40
0
0 50 100 150 200
Tmb C)
Pder = P-------P----t--o---t------- × 100%
t o t ( 25 °C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
200
ID
(A)
150
03ng54
100
Capped at 75 A due to package
50
0
25 50 75 100 125 150 175 200
Tmb (ºC)
VGS 5 V
Fig 2. Continuous drain current as a function of
mounting base temperature.
103
ID
(A)
102
10
Limit RDSon = VDS/ID
Capped at 75 A due to package
DC
03ng55
tp = 10 µs
100 µs
1 ms
10 ms
100 ms
1
10-1
1
10 102
VDS (V)
Tmb = 25 °C; IDM single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10277
Product data
Rev. 02 — 8 October 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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BUK95/964R2-55B
TrenchMOS™ logic level FET
4. Thermal characteristics
Table 3: Thermal characteristics
Symbol Parameter
Rth(j-mb) thermal resistance from junction to
mounting base
Rth(j-a) thermal resistance from junction to
ambient
SOT78
SOT404
Conditions
Figure 4
Min Typ Max Unit
- - 0.5 K/W
vertical in still air
mounted on a printed circuit board; minimum
footprint
-
-
60 -
50 -
K/W
K/W
4.1 Transient thermal impedance
1
Zth(j-mb)
(K/W)
10-1
10-2
δ = 0.5
0.2
0.1
0.05
0.02
single shot
10-3
10-6
10-5
10-4
10-3
10-2
03ng56
P
δ
=
tp
T
tp
T
t
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 10277
Product data
Rev. 02 — 8 October 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
4 of 15



BUK954R2-55B datasheet pdf
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