BUK9516-55A Datasheet PDF - NXP Semiconductors

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BUK9516-55A
NXP Semiconductors

Part Number BUK9516-55A
Description TrenchMOS stransistor Logic level FET
Page 12 Pages


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BUK9516-55A
N-channel TrenchMOS logic level FET
Rev. 02 — 21 April 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
„ AEC Q101 compliant
„ Low conduction losses due to low
on-state resistance
1.3 Applications
„ Automotive and general purpose
power switching
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter
VDS drain-source voltage
ID drain current
Ptot total power dissipation
Static characteristics
RDSon
drain-source on-state
resistance
Avalanche ruggedness
EDS(AL)S
non-repetitive
drain-source avalanche
energy
Conditions
Tj 25 °C; Tj 175 °C
Tmb = 25 °C
VGS = 10 V; ID = 25 A;
Tj = 25 °C
VGS = 5 V; ID = 25 A;
Tj = 25 °C
ID = 49 A; Vsup 25 V;
RGS = 50 ; VGS = 5 V;
Tj(init) = 25 °C; unclamped
Min Typ Max Unit
- - 55 V
- - 66 A
- - 138 W
- 10 15 m
- 12.5 16 m
- - 120 mJ



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NXP Semiconductors
BUK9516-55A
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G gate
D drain
S source
D mounting base; connected to drain
Simplified outline
mb
Graphic symbol
D
G
mbb076 S
3. Ordering information
123
SOT78A (TO-220AB)
Table 3. Ordering information
Type number
Package
Name
BUK9516-55A
TO-220AB
4. Limiting values
Description
plastic single-ended package; heatsink mounted; 1 mounting
hole; 3-lead TO-220AB
Version
SOT78A
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
VDGR
VGS
ID
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
VGSM
peak gate-source voltage
Source-drain diode
Conditions
Tj 25 °C; Tj 175 °C
RGS = 20 k
Tmb = 100 °C
Tmb = 25 °C
Tmb = 25 °C; pulsed
Tmb = 25 °C
pulsed; tp 50 µs
IS source current
ISM peak source current
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
Tmb = 25 °C
pulsed; Tmb = 25 °C
ID = 49 A; Vsup 25 V; RGS = 50 ;
VGS = 5 V; Tj(init) = 25 °C; unclamped
BUK9516-55A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 21 April 2011
Min Max Unit
- 55 V
- 55 V
-10 10 V
- 46 A
- 66 A
- 263 A
- 138 W
-55 175 °C
-55 175 °C
-15 15 V
- 66 A
- 263 A
- 120 mJ
© NXP B.V. 2011. All rights reserved.
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NXP Semiconductors
BUK9516-55A
N-channel TrenchMOS logic level FET
100
Pder
(%)
80
60
40
20
0
0
003aaf348
40 80 120 160 200
Tmb (°C)
100
ID
(%)
80
60
40
20
0
0
003aaf349
40 80 120 160 200
Tmb (°C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
Fig 2.
VGS 5 V
Normalized continuous drain current as a
function of mounting base temperature
103
IDM
(A)
RDS(on) = VDS / ID
102
D.C.
10
003aaf350
tp = 10 μs
100 μs
1 ms
10 ms
100 ms
100
WDSS
(%)
80
60
40
20
003aaf363
1
1 10 102
VDS (V)
Tmb = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
0
20 60 100 140 180
T(mb) (°C)
ID = 75 A
Fig 4. Normalised drain-source non-repetitive
avalanche energy as a function of
mounting-base temperature
BUK9516-55A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 21 April 2011
© NXP B.V. 2011. All rights reserved.
3 of 12



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NXP Semiconductors
BUK9516-55A
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Rth(j-a)
Thermal characteristics
Parameter
Conditions
thermal resistance from junction to mounting
base
thermal resistance from junction to ambient in free air
Min Typ Max Unit
- - 1.1 K/W
- 60 - K/W
10
Zth(j-mb)
(K/W)
1 δ = 0.5
0.2
003aaf351
101 0.1
0.05
0.02
P
tp
δ=
T
102
0
103
106
105
104
103
102
tp
T
101
t
1 10
tp (s)
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9516-55A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 21 April 2011
© NXP B.V. 2011. All rights reserved.
4 of 12



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BUK9516-55A N-channel TrenchMOS logic level FET BUK9516-55A
NXP Semiconductors
BUK9516-55A pdf

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