BD9888F Datasheet PDF - Rohm

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BD9888F
Rohm

Part Number BD9888F
Description DC-AC Inverter Control IC
Page 5 Pages


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1/4
STRUCTURE
NAME OF PRODUCT
Silicon Monolithic Integrated Circuit
DC-AC Inverter Control IC
TYPE BD9888F、BD9888FV
FUNCTION
・2ch control with Push-Pull
・Lamp current and voltage sense feed back control
・Sequencing easily achieved with Soft Start Control
・Short circuit protection with Timer Latch
・Under Voltage Lock Out
・Short circuit protection with over voltage
・Mode-selectable the operating or stand-by mode by stand-by pin
・Synchronous operating the other BD9888F or BD9888FV ICs
・BURST mode controlled by PWM and DC input
・Short circuit protection with voltage difference detection
○Absolute Maximum Ratings(Ta = 25℃)
Parameter
Symbol
Limits
Unit
Supply Voltage
VCC 15
V
Operating Temperature Range
Topr
-40~+90
Storage Temperature Range
Tstg
-55~+125
Power Dissipation
Pd
600*1(BD9888F)
850*2(BD9888FV)
mW
Maximum Junction Temperature Tjmax
+125
*1Pd derate at 6.0mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
*2Pd derate at 8.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇Recommended operating condition
Parameter
Supply voltage
CT oscillation frequency
BCT oscillation frequency
Symbol
VCC
fCT
fBCT
Limits
5.0~14.0
20~150
0.05~0.50
Unit
V
kHz
kHz
Status of this document
The Japanese version of this document is the official specification.
Please use the translation version of this document as a reference to expedite understanding of the official version.
If these are any uncertainty in translation version of this document, official version takes priority.
REV. A



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○Electric Characteristics(Ta=25℃,VCC=7V)
Parameter
((WHOLE DEVICE))
Operating current
Stand-by current
((OVER VOLTAGE DETECT))
FB over voltage detect voltage
((STAND BY CONTROL))
Stand-by voltage H
Stand-by voltage L
Stand-by hysteresis
((TIMER LATCH))
Timer Latch voltage
Timer Latch current
((BURST MODE))
BOSC Max voltage
BOSC Min Voltage
BOSC constant current
BOSC frequency
((OSC BLOCK))
OSC constant current
OSC Max voltage
OSC Min voltage
MAX DUTY
Soft start current
IS COMP detect Voltage
SS COMP detect voltage
SRT ON resistance
((UVLO BLOCK))
Operating voltage
Shut down voltage
((REG BLOCK))
REG output voltage
REG source current
VREF voltage
((FEED BACK BLOCK))
IS threshold voltage
VS threshold voltage
IS source current 1
IS source current 2
VS source current
((OUTPUT BLOCK))
NAch output voltage H
NBch output voltage H
NAch output voltage L
NBch output voltage L
NAch output sink resistance
NAch output source resistance
NBch output sink resistance
NBch output source resistance
Drive output frequency
((COMP BLOCK))
Under voltage detect
Voltage difference detect
Symbol
Icc1
Icc2
Vovf
VstH
VstL
⊿Vst
Vcp
Icp
VburH
VburL
IBCT
fBCT
ICT
VoscH
VoscL
MAXDUTY
Iss
Visc
Vss
RSRT
VuvloH
VuvloL
VREG
IREG
VREF
Vis
Vvs
Iis1
Iis2
Ivs
VoutNAH
VoutNBH
VoutNAL
VoutNBL
RsinkNA
RsourceNA
RsinkNB
RsourceNB
fOUT
VCOMPL
⊿VCOMP
MIN.
2.20
1.6
-0.3
0.08
1.9
0.5
1.94
0.4
1.35/BRT
266
1.35/RT
1.8
0.3
44
1.0
0.45
2.0
4.100
3.900
3.038
5.0
1.225
1.225
1.220
13.0
VCC-0.3
VCC-0.3
58.5
0.620
0.40
(This product is not designed to be radiation-resistant.)
Limits
TYP.
11.0
2
2.40
0.18
2.0
1.0
2.0
0.5
1.5/BRT
280
1.5/RT
2.0
0.5
46.5
2.0
0.50
2.2
200
4.300
4.100
3.100
1.250
1.250
1.250
20.0
VCC-0.1
VCC-0.1
0.1
0.1
5
8
5
8
60.0
0.640
0.45
MAX.
17.0
10
2.60
VCC
0.8
0.28
2.1
1.5
2.06
0.6
1.65/BRT
294
1.65/RT
2.2
0.7
49
3.0
0.55
2.4
400
4.500
4.300
3.162
1.275
1.275
1.280
1.5
27.0
1.0
0.3
0.3
10
16
10
16
61.5
0.660
0.5
2/4
Unit
Conditions
mA CT=0.5V
μA
V
V System ON
V System OFF
V
V
μA
V fBCT=0.2kHz
V fBCT=0.2kHz
A
Hz BRT=33kΩ、BCT=0.050μF
A
V fCT=60kHz
V fCT=60kHz
% fCT=60kHz
μA
V
V
Ω
V
V
V
mA
V VREF=Open
V
V
μA DUTY=2.0V
μA DUTY=0V、IS=0.5V
μA
V
V
V
V
Ω Isink = 10mA
Ω Isource = 10mA
Ω Isink = 10mA
Ω Isource = 10mA
KHz RT=18kΩ、CT=395pF
V
V |VCOMPA-VCOMPB|
REV. A



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〇Package Dimensions
(Include BURR 18.85)
BD9888F
Device Mark
3/4
(Include BURR 10.35)
BD9888FV
SOP28 (unit:mm)
Lot No.
SSOP-B28 (unit:mm)
〇Block Diagram
VCC REG VREF
REG
BLOCK
STB
STB
BLOCK
SYSTEM ON/OFF
SS
FB1
IS1 F/B
VS1 BLOCK①
SS
CT
FB2
IS2 F/B
VS2 BLOCK②
SS
CT
GND
PROTECT
BLOCK
SCP SRT
〇Pin Description
CT RT
BRT BCT
DUTY
OSC
BOSC
DUTY
BLOCK
PWM
BLOCK①
PWM
BLOCK②
UVLO
BLOCK
VCC
LOGIC
BLOCK
LOGIC
BLOCK
VCC
OUTPUT
BLOCK①
VCC
OUTPUT
BLOCK②
COMP BLOCK
VOLTAGE
VOLTAGE
DIFFERENCE
DIFFERENCE
DETECT BLOCK DETECT BLOCK
①②
NA1
NB1
NA2
NB2
PGND
COMPA1
COMPA2
COMPB1
COMPB2
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin
Name
DUTY
BRT
BCT
RT
SRT
CT
GND
FB1
IS1
VS1
FB2
IS2
VS2
VREF
COMPA1
STB
COMPB1
COMPA2
COMPB2
REG
SS
SCP
NA2
NB2
PGND
NB1
NA1
Vcc
Function
Control PWM mode and BURST mode
External resistor from BRT to GND for
adjusting the BURST triangle oscillator
External capacitor from BCT to GND for
adjusting the BURST triangle oscillator
External resistor from SRT to RT for
adjusting the triangle oscillator
External resistor from SRT to RT for
adjusting the triangle oscillator
External capacitor from CT to GND for
adjusting the triangle oscillator
GROUND
Error amplifier output①
Error amplifier input①
Error amplifier input②
Error amplifier output②
Error amplifier input③
Error amplifier input④
Reference voltage
Voltage difference or under voltage
detect for 1ch
Stand-by switch
Voltage difference or under voltage
detect for 1ch
Voltage difference or under voltage
detect for 2ch
Voltage difference or under voltage
detect for 2ch.
Internal regulator output
External capacitor from SS to GND for
Soft Start Control
External capacitor from SCP to GND for
Timer Latch
FET driver for 2ch
FET driver for 2ch
Ground for FET drivers
FET driver for 1ch
FET driver for 1ch
Supply voltage input
REV. A



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4/4
NOTE FOR USE
1. When designing the external circuit, including adequate margins for variation between external devices
and IC. Use adequate margins for steady state and transient characteristics.
2. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is
within recommended operating range. The standard electrical characteristic values cannot be guaranteed
at other voltages in the operating ranges, however the variation will be small.
3. Mounting failures, such as misdirection or miscounts, may harm the device.
4. A strong electromagnetic field may cause the IC to malfunction.
5. The GND pin should be the location within ±0.3V compared with the PGND pin.
6. BD9888F and BD9888FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown
circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not
designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed.
7. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become
significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical
countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings.
8. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage
is switching. Make sure to leave adequate margin for this IC variation.
9. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch.
10. By STB voltage, BD9888F and BD9888FV are changed to 2 states. Therefore, do not input STB pin voltage
between one state and the other state (0.8~1.6).
11. The pin connected a connector need to connect to the resistor for electrical surge destruction.
This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins.
A P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
12.This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A
P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
Resistance
(PinA)
P
P
N
P
P substrate
GND
Parasitic diode
Transistor (NPN)
(PinB)
B
C
E
N
GND
N
P substrate
GND
Parasitic diode
N
(PinB)
(PinA)
Parasitic diode
B C
E
GND
GND
Other adjacent components Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. A



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Related : Start with BD9888 Part Numbers by
BD9888F DC-AC Inverter Control IC BD9888F
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BD9888FV DC-AC Inverter Control IC BD9888FV
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BD9888FV pdf

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