BD429C Datasheet PDF - DEI

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BD429C
DEI

Part Number BD429C
Description Line Driver
Page 13 Pages


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Device
Engineering
Incorporated
385 E. Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
BD429/BD429A/BD429B/BD429C
ARINC 429/RS-422 Line Driver
Integrated Circuit
www.DataSFheeeta4Utu.cormes:
ARINC 429 Line Driver for HI speed (100 kHz) and LOW speed (12.5 kHz) data rates
Pin for Pin replacement part for industry standard ARINC 429 Line Drivers
Available in a 16 Pin SOIC (WB), 16 Pin CERDIP, 16 Pin Plastic Dip,
16 Lead Ceramic SOP, 28L CLCC and 28L PLCC
Low EMI RS-422 line driver mode for data rates up to 100 kHz
Adjustable slew rates via two external capacitors
Inputs are TTL and CMOS compatible
Low quiescent power of 125mW (typical)
Programmable output differential range via VREF pin
Outputs are fused for failsafe overvoltage protection
Drives full ARINC load of 400and 30,000pF
Extended (-55°C/+85°C) and Military (-55°C/+125°C) temperature ranges
100% Final Testing
Figure 1: BD429 Block Diagram
© 2008 Device Engineering Incorporated
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DS-MW-00429-01 Rev. C
8/1/08



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General Description:
The BD429 ARINC Line Driver Circuit is a bipolar monolithic IC designed to meet the requirements of several general
aviation serial data bus standards. These include the differential bipolar RZ types such as ARINC 429, ARINC 571,
and ARINC 575, as well as the differential NRZ types such as the RS-422 standard.
Functional Description:
Modes: The BD429 operates in either a 429 mode or a 422 mode as controlled by the 429/422´ pin.
429 Mode: In 429 mode, the serial data is presented on the DATA(A) and DATA(B) inputs in the dual rail format
defined in the MARK 33 Digital Information Transfer System – ARINC Specification 429-10. The driver is enabled by
the SYNC and CLOCK inputs. The output voltage level is programmed by the VREF input and is normally tied to
+5VDC along with V1 to produce output levels of +5 volts, 0 volts, and –5 volts on each output for ±10 volts
differential outputs. * See Figure 4.
www.DataSheet44U2.2coMmode: In 422 mode, the serial data is presented on DATA(A) input. The driver is enabled by the SYNC and
CLOCK inputs. The outputs swings between 0 volts and +5 volts if VREF is at +5VDC. *See Figure 5.
Output Resistance: The driver output resistance is 75±20% at room temperature; 37.5on each output. The
outputs are also fused for failsafe protection against shorts to aircraft power. The output slew rate is controlled by
external timing capacitors on CA and CB. Typical values are 75pF for 100 KHz data and 500pF for 12.5 KHz data.
Table 1: Truth Table
© 2008 Device Engineering Incorporated
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V REF 1
NC 2
SYNC 3
DATA(A) 4
CA 5
AOUT 6
-V 7
www.DataSheet4U.comGND 8
16 V1
15 429/422'
14 CLOCK
13 DATA(B)
12 C B
11 BOUT
10 NC
9 +V
Figure 3: DIP, SOIC & CSOP Pinout
NC
DATA(A)
NC
NC
CA
NC
NC
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
CLOCK
NC
DATA(B)
CB
NC
NC
NC
Figure 2: PLCC & CLCC Pinout
Pin Name
VREF
Table 2: Pin Descriptions
Description
Analog Input. The voltage on VREF sets the output voltage levels on AOUT and BOUT. The output
logic levels swing between +VREF, 0 volts, and –VREF volts.
NC No Connect
SYNC
Logic input. Logic 0 forces outputs to NULL state. Logic 1 enables data transmission.
DATA(A)
DATA(B)
CA
CB
AOUT
BOUT
Logic inputs. These signals contain the Serial Data to be transmitted on the ARINC 429 data bus.
Refer to Figure 4and Figure 5.
Analog Nodes. External timing capacitors are tied from these points to ground to establish the
output signal slew rate. Typical CA = CB = 75pF for 100 kHz data and CA = CB = 500pF for 12.5
kHz data. *
Outputs. These are the line driver outputs which are connected to the aircraft serial data bus.
-V Negative Supply Input. –15VDC nominal.
GND
Ground.
+V Positive Supply Input. +15VDC nominal.
CLOCK Logic input. Logic 0 forces outputs to NULL state. Logic 1 enables data transmission.
429/422'
Logic Input. Mode control for ARINC 429 and RS-422 modes. An internal 10Kpull up resistor
keeps the chip in ARINC 429 mode when there is no external connection. This creates a default
logic 1, enabling the ARINC 429 mode. A forced logic 0 enables the RS-422 mode.
V1 Logic Supply Input. +5VDC nominal.
*CA and CB pin voltages swing between ±5 volts. Any electronic switching of the capacitor on the pins must not inhibit the full voltage swings.
© 2008 Device Engineering Incorporated
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DS-MW-00429-01 Rev. C
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Table 3: Absolute Maximum Ratings
PARAMETER
SYMBOL
Voltage between pins +V and –V
V1 Maximum Voltage
VREF Maximum Voltage
DATA(A) Max Input Voltage
DATA(B) Max Input Voltage
Lead Soldering Temperature (10 sec duration)
Storage Temperature
V1
VREF
VDATA(A)
VDATA(B)
TSLD
TSTG
Max Junction Temperature
Ceramic Package & Plastic Package short term operation
Max Junction Temperature
Plastic Package Limit (prolonged operation)
www.DataSheet4UO.cuotmput Short Circuit Duration
TJ MAX1
TJ MAX2
Output Over-Voltage Protection
RATING
40
7
6
(GND-0.3V) to
(V1 + 0.3V)
280
-65 to +150
+175
+145
See Note 1
See Note 2
UNITS
V
V
V
V
oC
oC
oC
oC
Power Dissipation
See Table 5 below
Notes.
1. One output at a time can be shorted to ground indefinitely.
2. Both outputs are fused at between 0.5 Amp DC and 1.0 Amp DC to prevent an over-voltage fault from
coupling onto the system power bus.
Table 4: Operating Range
PARAMETER
SYMBOL
Positive Supply Voltage
+V
Negative Supply Voltage
-V
V1 V1
VREF (For ARINC 429)
VREF
VREF (For other applications)
VREF
Operating Temperature (Plastic Package)
TA
Operating Temperature (Ceramic Package)
TA
MIN
+11.4
-11.4
+4.75
+4.75
+3
-55
-55
TYP
+5
+5
MAX
16.5
-16.5
+5.25
+5.25
+6
+85
+125
UNITS
VDC
VDC
VDC
VDC
VDC
°C
°C
Thermal Management
Device power dissipation varies greatly as a function of data rate, load capacitance, data duty cycle, and supply voltage.
Proper thermal management is important in designs operating at the HI speed data rate (100KBS) with high capacitive
loads and high data duty cycles.
Power dissipation may be estimated from Table 5 “Power Dissipation Table”. Device power dissipation (Pd) is indicated
for 100% data duty cycle with no word gap null times and should be adjusted for the appropriate data duty cycle (DC).
Pd(application) = DC * [Pd(table) - 145mW] + 145mW, where DC is the application data duty cycle, Pd(table) is the Pd
from the table for the indicated data rate and bus load, and 145mW is the quiescent power. The application’s data duty
cycle (DC) for 100KBS operation is calculated as:
DC = (total bits transmitted in 10 sec period / 1,000,000) =
(32 x total ARINC words transmitted in 10 sec period / 1,000,000).
Heat transfer from the IC package should be maximized. Use maximum trace width on all power and signal connections
at the IC. Place vias on the signal/power traces close to the IC to maximize heat flow to the internal power planes. If
possible, design a solid heat spreader land under and beyond the IC to maximize heat flow from the device.
© 2008 Device Engineering Incorporated
Page 5 of 14
DS-MW-00429-01 Rev. C
8/1/08



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