BD3531F Datasheet PDF - Rohm

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BD3531F
Rohm

Part Number BD3531F
Description Termination Regulator
Page 19 Pages


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Datasheet
Termination Regulator for DDR-SDRAMs
BD3531F
General Description
BD3531F is a termination regulator that complies with
JEDEC requirements for DDR-SDRAM. This linear
power supply uses a built-in N-channel MOSFET and
high-speed OP-AMPS specially designed to provide
excellent transient response. It has a sink/source
current capability up to 1.5A and has a power supply
bias requirement of 5.0V for driving the N-channel
MOSFET. By employing an independent reference
voltage input (VDDQ) and a feedback pin (VTTS), this
termination regulator provides excellent output voltage
accuracy and load regulation as required by JEDEC
standards. Additionally, BD3531F has a reference
power supply output (VREF) for DDR-SDRAM or for
memory controllers. Unlike the VTT output that goes to
“Hi-Z” state, the VREF output is kept unchanged when
EN input is changed to “Low”, making this IC suitable
for DDR-SDRAM under “Self Refresh” state.
Features
Incorporates a Push-Pull Power Supply for
Termination (VTT)
Incorporates a Reference Voltage Circuit (VREF)
Incorporates an Enabler
Incorporates an Undervoltage Lockout (UVLO)
Incorporates a Thermal Shutdown Protector (TSD)
Compatible with Dual Channel (DDR-II)
Applications
Power supply for DDR I/II - SDRAM
Key Specifications
Termination Input Voltage Range: 1.0V to 5.5V
VCC Input Voltage Range:
4.5V to 5.5V
Output Voltage:
1/2xVVDDQ V(Typ)
Output Current:
1.5A(Max)
High Side FET ON-Resistance:
0.4Ω(Typ)
Low side FET ON-Resistance:
0.4Ω(Typ)
Standby Current:
0.8mA (Typ)
Operating Temperature Range: -10°C to +100°C
Package
W(Typ) x D(Typ) x H(Max)
SOP8
5.00mm x 6.20mm x 1.71mm
Typical Application Circuit, Block Diagram
VCC
VDDQ
VTT_IN
VCC
Reference
Block
VDDQ
VCC
50kΩ
UVLO
VCC
50kΩ
UVLO
Enable
EN
Thermal
Protection
TSD
GND
VCC
VTT_IN
TSD
VCC EN
UVLO
TSD
EN
UVLO
VTT
VTTS
VREF
VTT
½x
VDDQ
Product structureSilicon monolithic integrated circuit
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© 2015 ROHM Co., Ltd. All rights reserved.
TSZ2211114001
This product has no designed protection against radioactive rays
1/15
TSZ02201-0J2J0A900950-1-2
02.Nov.2015 Rev.001



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BD3531F
Pin Configuration
TOP VIEW
GND 1
EN 2
VTTS 3
VREF 4
8 VTT
7 VTT_IN
6 VCC
5 VDDQ
Pin Descriptions
Pin No. Pin Name
Pin Function
1 GND GND Pin
2 EN Enable Input Pin
3 VTTS Detector Pin for Termination Voltage
4 VREF Reference Voltage Output Pin
5 VDDQ Reference Voltage Input Pin
6 VCC VCC Pin
7 VTT_IN Termination Input Pin
8 VTT Termination Output Pin
Description of Blocks
1. VCC
The VCC pin is for the independent power supply input that operates the internal circuit of the IC. It is the voltage at
this pin that drives the IC’s amplifier circuits. The VCC input ranges 5V and maximum current consumption is 4mA. A
bypass capacitor of 10μF or so should be connected to this pin when using the IC in an application circuit.
2. VDDQ
This is the power supply input pin for an internal voltage divider network. The voltage at VDDQ is halved by two 50kΩ
internal voltage-divider resistors and the resulting voltage serves as reference for the VTT output. Since VTT =
1/2VDDQ, the JEDEC requirement for DDR-SDRAM can be satisfied by supplying the correct voltage to VDDQ.
Noise input should be avoided at the VDDQ pin as it is also included by the voltage-divider at the output. An RC filter
consisting of a resistor and a capacitor (220Ω and 2.2μF, for instance,) may be used to reduce the noise input but
make sure that it will not significantly affect the voltage-divider’s output.
3. VTT_IN
VTT_IN is the power supply input pin for the VTT output. Input voltage may range from 1.0V to 5.5V, but
consideration must be given to the current limit dictated by the ON-Resistance of the IC and to the change in allowable
loss due to input/output voltage difference.
Generally, the following voltages are supplied:
DDR I
VVTT_IN =2.5V
DDRII
VVTT_IN =1.8V
Take note that a high-impedance voltage input at VTT_IN may result in oscillation or degradation in ripple rejection, so
connecting a 100μF capacitor with minimal change in capacitance to VTT_IN terminal is recommended. However,
this impedance may depend on the characteristics of the power supply input and the impedance of the PC board wiring,
which must be carefully checked before use.
4. VREF
BD3531F provides a constant voltage, VREF, which is independent from the VTT output and can serve as reference
input for memory controllers and DRAMs. The voltage level of VREF is kept constant even if the EN pin is at “Low”
level, making the use of this IC compatible with the “Self Refresh” state of DRAMs.
In order to stabilize the output voltage, connecting the correct combination of capacitor and resistor to VREF is
necessary. For this purpose, a combination of 1.0μF to 2.2μF ceramic capacitor, characterized by minimal variation in
capacitance, and a 0.5Ω to 2.2Ω phase compensating resistor is recommended.
5. VTTS
VTTS is a sense pin for the load regulation of the VTT output voltage. In case the wire connecting VTT pin and the load
is too long, connecting VTTS pin to the part of the wire nearer to the load may improve load regulation.
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© 2015 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
2/15
TSZ02201-0J2J0A900950-1-2
02.Nov.2015 Rev.001



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BD3531F
Description of Blocks continued
6. VTT
This is the output pin for the DDR memory termination voltage and it has a sink/source current capability of ±1.5A. VTT
voltage tracks the voltage at VDDQ pin divided in half. The output is turned OFF when EN pin is “Low” or when either
the VCC UVLO or the thermal shutdown protection function is activated.
Always connect a capacitor to VTT pin for loop gain and phase compensation and for reduction in output voltage
variation in the event of sudden load change. Be careful in choosing the capacitor as insufficient capacitance may
cause oscillation and high ESR (Equivalent Series Resistance) may result in increased output voltage variation during
a sudden change in load. Using a low-ESR ceramic capacitor, however, may reduce the loop gain and phase margin
and may cause oscillation. But this effect can be lessened by connecting a resistor in series with the capacitor. A 220μF
functional polymer capacitor (OS-CON, POS-CAP, NEO-CAP) is recommended, though ambient temperature and
other conditions should also be considered.
7. EN
A “High” input of 2.0V or higher to EN turns ON the VTT output. A “Low” input of 0.8V or less, on the other hand, turns
VTT to a Hi-Z state. With a “Low” EN input, however, the VREF output remains ON, provided that sufficient VCC and
VDDQ voltages have been established.
Absolute Maximum Ratings
Parameter
Symbol
Limit
Unit
Input Voltage
EN Input Voltage
Termination Input Voltage
VDDQ Reference Voltage
VCC
VEN
VVTT_IN
VVDDQ
7 (Note 1)
7 (Note 1)
7 (Note 1)
7 (Note 1)
V
V
V
V
Output Current
Power Dissipation1
IVTT
Pd1
1.5
0.56 (Note 2)
A
W
Power Dissipation2
Pd2
0.69 (Note 3)
W
Operating Temperature Range
Topr
-10 to +100
°C
Storage Temperature Range
Tstg
-55 to+150
°C
Maximum Junction Temperature
Tjmax
+150
°C
(Note 1) Should not exceed Pd.
(Note 2) Derate by 4.48mW/°C for Ta over 25°C (With no heat sink).
(Note 3) Derate by 5.52mW/°C for Ta over 25°C (When mounted on a board 70mm x 70mm x 1.6mm Glass-epoxyPCB).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. In addition, it is impossible to predict all destructive situations such as
short-circuit modes, open circuit modes, etc. Therefore, it is important to consider circuit protection measures, like adding a fuse, in case the IC is operated in a
special mode exceeding the absolute maximum ratings.
Recommended Operating Conditions (Ta=25°C)
Parameter
Symbol
Min
Input Voltage
VCC 4.5
Termination Input Voltage
VVTT_IN
1.0
EN Input Voltage
VEN -0.3
Max
5.5
5.5
+5.5
Unit
V
V
V
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© 2015 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
3/15
TSZ02201-0J2J0A900950-1-2
02.Nov.2015 Rev.001



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BD3531F
Electrical Characteristics
(Unless otherwise noted, Ta=25°C VCC=5V VEN=3V VVDDQ=2.5V VVTT_IN=2.5V)
Parameter
Symbol
Standard Value
Min Typ Max
Standby Current
IST - 0.8 1.6
Bias Current
ICC - 2 4
[Enable]
Hi Level Enable Input Voltage
VENHI
2
- 5.5
Low Level Enable Input Voltage VENLOW
-0.3
-
+0.8
Enable Pin Input Current
IEN - 7 10
[Termination]
Termination Output Voltage
VVTT
VVREF
-30mV
VVREF
VVREF
+30mV
Source Current
Sink Current
Load Regulation
Line Regulation
Upper Side ON-Resistance
Lower Side ON-Resistance
[Input of Reference Voltage]
Input Impedance
[Reference voltage]
Output Voltage1
IVTT+
IVTT-
VVTT
Reg.l
RHRON
RLRON
ZVDDQ
VVREF1
Output Voltage2
Source Current
Sink Current
[UVLO]
UVLO OFF Voltage
Hysteresis Voltage
(Note 4) No tested on outgoing inspection
VVREF2
IVREF+
IVREF-
VUVLO
VUVLO
1.5
-
-
-
-
-
-
½ x VVDDQ
-30m
½ x VVDDQ
-40m
10
-
4.2
100
-
-
-
20
0.4
0.4
100
½x
VVDDQ
½x
VVDDQ
20
-20
4.35
160
-
-1.5
40
40
0.8
0.8
-
½ x VVDDQ
+30m
½ x VVDDQ
+40m
-
-10
4.5
220
Unit Conditions
mA VEN=0V
mA
V
V
µA VEN=3V
V
IOUT=-1.5A to +1.5A
Ta=0°C to +100 °C (Note 4)
A
A
mV IOUT=-1.5A to +1.5A
mV VCC=4.5V to 5.5V
Ω
Ω
V IVREF=0mA
V
IVREF=-10mA to +10mA
Ta=0°C to 100°C (Note 4)
mA
mA
V VCC : Sweep up
mV VCC : Sweep down
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© 2015 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
4/15
TSZ02201-0J2J0A900950-1-2
02.Nov.2015 Rev.001



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