AN1515 Datasheet PDF - STMicroelectronics

www.Datasheet-PDF.com

AN1515
STMicroelectronics

Part Number AN1515
Description Digital Output Angular Accelerometer
Page 13 Pages


AN1515 datasheet pdf
Download PDF
AN1515 pdf
View PDF for Mobile


No Preview Available !

AN1515
APPLICATION NOTE
LIS1R02 (L6671):
A DIGITAL OUTPUT ANGULAR ACCELEROMETER
by F. Pasolini
1 INTRODUCTION
www.DataSheet4UT.choem LIS1R02 is a complete rotational accelerometer system based on a capacitive sensor that uses MEMS
technology, and a set of accompanying electronics that produces a digital output. The device is interfaced to
external hardware using a standard 3-wire serial interface that allows internal registers to be written and rota-
tional acceleration samples to be read.
The MEMS structure consists of a rotor and stator assembly in which capacitive variations occur when the rel-
ative position of the rotor with respect to the stator changes. These capacitive variations are on the order of 50
x 10-18 farads. The MEMS structure also includes actuation electrodes that allow the rotor position to be driven
externally by the processing electronics.
The electronic processing circuitry processes the capacitive variations that occur between the MEMS rotor and
stator. A SigmaDelta architecture is implemented that works to continually restore the rotor to nominal position.
The control effort, or the signal that drives the rotor to nominal, represents the rotational acceleration that is
present at the system location. This control effort is a binary bit stream that is decimated by the electronics to
provide a noise-reduced output
Gain and offset adjustments are applied to the decimated bit stream to produce the acceleration samples. Ac-
celerometer samples then are clocked into a four-deep data FIFO within the IC. The decimation and FIFO stag-
es are clocked in a free-running manner based on the selection of either an internal or external clock source.
1.1 Choosing an External Clock Source
Designers who will use the LIS1R02 to select the clock source which can be either from the CLK_IN pin, from
the internal oscillator or generated by using an embedded PLL.
When the CLK pin is selected as clock source, the designer has the ability to control the rate at which rotational
acceleration samples are generated within the LIS1R02. It takes exactly 224 CLK_IN cycles to generate one
new rotational acceleration sample, therefore the formula for determining the optimal frequency of the CLK_IN
signal is as follows:
Fout
=
-F---C----L---K----I--N--
224
(Eq. 2.1)
where FCLKIN is the frequency of the clock signal that is applied to the CLK_IN pin and Fout si the frequency
at which samples are produced.
If it is possible for the designer to implement a CLK_IN signal that satisfies equation 2.1 perfectly, then the de-
vice will generate one new acceleration sample at the desired rate (1/Ts). In practice, most designers will find it
difficult to supply a clock whose frequency satisfies equation 2.1. Generally, the designer will be restricted to
using a signal for CLK_IN that only approximates equation 2.1. In this case, the acceleration samples will be
generated at a rate that differs from the desired sample rate. The inclusion of the on-chip FIFO data buffer allows
for the proper handling of the accelerometer samples that are produced by the device.
In the case where:
FCLKIN
<
2----2---4--
Ts
(Eq. 2.2)
February 2002
1/12



No Preview Available !

AN1515 APPLICATION NOTE
a double sample will occur at a regular interval. The interval is a function of the difference between the LIS1R02
sample generation rate and the desired sampling rate (1/Ts). This interval, in units of servo sample periods, can
be determined with the expression:
Tdouble
=
----------------T----1-----s-------------------
-F---C----L---K----I--N--
224
T--1---s-
(Eq. 2.3)
For example, if FCLKIN = 2.00 MHz and Ts = 124 µs, then the FIFO will contain two valid samples on approxi-
mately every 9.333 samples.
w w w . D a tCaonSverhseely,eif t 4 U . c o m
FCLKIN
>
2----2---4--
Ts
(Eq. 2.4)
then a missing or empty sample will occur at a regular rate.
In either case, the handling of the samples must be done carefully to fully minimize the noise in the system.
For the purpose of obtaining multiple samples per servo period, the designer can choose a CLK_IN frequency
that is approximately equal to an integer multiple of the product seen in equation 2.1.
FCLKIN
=
N
×
2----2---4--
Ts
(Eq. 2.5)
In this case, the accelerometer samples will be generated at a rate of approximately N samples per desired sam-
ple period, where N could be equal to 1, 2, 3, or 4. The designer must note, however, that the maximum fre-
quency of CLK_IN, according to specification, is 6MHz.
When the internal oscillator is selected, the samples will be generated in a free-running manner, based on the
internal clock rate. With the default settings, samples are generated at a rate of approximately 20KHz.
To allow the production of data samples at a desired rate, a digital PLL has been embedded. In this case, the
formulas to be used to calculate the frequency of the signals stated in Figure 1 are:
Frefdiv = (---I--D---F--F--r--e-+--f---1----)
Frefdiv = (---I--D---F--F--r--e-+--f---1----)
(Eq. 2.6)
To allow the PLL to operate correctly, Fref must be at least equal to 5 KHz.
Fdco = Frefdiv(MF + 1) = Fref(-(--I-M-D----F-F----+-+----1-1---)-)
(Eq. 2.7)
Frefdiv = (---O-----DF----d-F--c---+o-----1----) = Fref (---I--D-----F-----+(---M--1---F-)--(--+O-----1-D---)-F-----+------1---)-
(Eq. 2.8)
For a better understanding of the IDF, ODF and MF terms, please refer to the PLL registers description.
2/12



No Preview Available !

AN1515 APPLICATION NOTE
Figure 1. Clock generation scheme
pin_CLK
Fosc
OSC
OPDN
.. Foscdiv
IOD[3:0]
0
1
CS0
www.DataSheet4U.com
SPE
x2
0
1
PLLT
0 Main CK
1
CS1
0 Fref
1
Frefdiv
.
.
PD
Fdco
DCO
.. Fosc
CS0 IDF[3:0]
..
ODF[1:0]
MF[9:0]
ADPLL
1
DSC
0 Reference signal
FIFO_Low Read
(from internal logic)
DSCR
1.2 Serial Interface
The Serial Interface interacts with the outside world with 3 wires: SPE, SPC and SPD. It is used to write the data
into the registers (REGISTERS block) which can also be read.
1.2.1 READ & WRITE REGISTER
Figure 2. Read & write protocol
SPE
SPC
SPD
RW AD3 AD2 AD1 AD0
ID2 ID1 ID0
D7 D6 D5 D4 D3 D2 D1 D0
3/12



No Preview Available !

AN1515 APPLICATION NOTE
SPE is the Serial Port Enable. It goes high at the start of the transmission and goes back low at the end. SPC
is the Serial Port Clock. It is stopped high when SPE is low (no transmission). SPD is the Serial Port Data. It is
driven by the falling edge of SPC. It should be captured at the rising edge of SPC.
The Read Register or Write Register command consists of 16 clocks or bits. A bit duration is the time between
two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the rising edge of SPE
and the last bit (bit 15) starts at the last falling edge of SPC just before the falling edge of SPE.
bit 0: RW bit. When 0, the data D(7:0) is written into the RAC. When 1, the data D(7:0) from the RAC is read. In
this case, the chip will drive SPD at the start of bit 8.
bit 1-3: chip ID. The chip ID for the RAC is ID(2:0)=110. The LIS1R02 accepts the command only when the ID
is valid (equal to 110).
www.DataSheet4Ub.citom4-7: address AD(3:0). This is the address field for the registers.
bit 8-15: data D(7:0). This is the data that will be written (read) into (from) the register which address is AD(3:0).
1.2.2 READ FIFO
Figure 3. Read FIFO protocol
SPE
SPC
SPD
RW AD3 AD2 AD1 AD0
ID2 ID1 ID0
D7-0 D6-0 ...... D0-0 D7-1 D6-1 ...... D0-1
The Read FIFO command consists of 24 clocks or bits:
bit 0: READ bit. The value is 1.
bit 1-3: chip ID. ID(2:0)=110.
bit 4-7: FIFO address. The FIFO has four registers grouped into two banks. The first bank consists of the first
and the second register. The first register is the one written first since the last read. The second bank consists
of the third and fourth register.
000x: address for the first bank
001x: address for the second bank
bit 8-23: FIFO data. The RAC puts out first the data of the first register of the bank starting with the MSB.
1.2.3 Notice
The serial interface allows the IC to work with the SPE line tied high.
The clock line has to be normally high (i.e. clock off-state = 1 as depicted in Figure 2.).
If the clock remains high beyond the time out period, the serial interface is reset. This feature allows a IC test to
run at very low frequency using narrow clock pulses. If a packet is not completed correctly, the normal high clock
will generate a port reset, flushing the data.
The timeout period is set to be 280*Tosc. Thus, supposing to have Fosc = 70 MHz, the timeout period will be 4µs.
4/12



AN1515 datasheet pdf
Download PDF
AN1515 pdf
View PDF for Mobile


Related : Start with AN151 Part Numbers by
AN1511 Low Voltage Gated Function Generator AN1511
Philips
AN1511 pdf
AN1512 All in one NE5230 AN1512
Philips
AN1512 pdf
AN1513 NE5205 A Cascadable Amplifier AN1513
Philips
AN1513 pdf
AN1515 Digital Output Angular Accelerometer AN1515
STMicroelectronics
AN1515 pdf
AN1516 Liquid Level Control Using a Pressure Sensor AN1516
Motorola
AN1516 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact