PERFORMANCE CHARACTERISTICS OF EPAD®
PRECISION MATCHED PAIR MOSFET FAMILY (cont.)
SUB-THRESHOLD REGION OF OPERATION
The gate threshold (turn-on) voltage VGS(th) of the EPAD MOSFET
is a voltage below which the MOSFET conduction channel rapidly
turns off. For analog designs, this gate threshold voltage directly
affects the operating signal voltage range and the operating bias
At a voltage below VGS(th), an EPAD MOSFET exhibits a turn-off
characteristic in an operating region called the subthreshold re-
gion. This is when the EPAD MOSFET conduction channel rapidly
turns off as a function of decreasing applied gate voltage. The con-
duction channel, induced by the gate voltage on the gate elec-
trode, decreases exponentially and causes the drain current to de-
crease exponentially as well. However, the conduction channel does
not shut off abruptly with decreasing gate voltage, but rather de-
creases at a fixed rate of about 104mV per decade of drain current
decrease. For example, for the ALD2108xx device, if the gate thresh-
old voltage is +0.20V, the drain current is 10µA at VGS = +0.20V.
At VGS = +0.096V, the drain current would decrease to 1µA. Ex-
trapolating from this, the drain current is about 0.1µA at
VGS = 0.00V, 1nA at VGS = -0.216V, and so forth. This subthresh-
old characteristic extends all the way down to current levels below
1nA and is limited by junction leakage currents.
At a drain current of “zero current” as defined and selected by the
user, the VGS voltage at that zero current can now be estimated.
Note that using the above example, with VGS(th) = +0.20V, the
drain current still hovers around 100nA when the gate is at ground
voltage. With a device that has VGS(th) = +0.40V (part number
ALD210804), the drain current is about 2nA when the gate is at
ground potential. Thus, in this case an input signal referenced to
ground can operate with a natural drain current of only 2nA internal
bias current, dissipating nano-watts of power.
LOW POWER AND NANOPOWER
When supply voltages decrease, the power consumption of a given
load resistor decreases as the square of the supply voltage. Thus,
one of the benefits in reducing supply voltage is to reduce power
consumption. While decreasing power supply voltages and power
consumption go hand-in-hand with decreasing useful AC bandwidth
and increased noise effects in the circuit, a circuit designer can
make the necessary tradeoffs and adjustments in any given circuit
design and bias the circuit accordingly for optimal performance.
With EPAD MOSFETs, a circuit that performs any specific function
can be designed so that power consumption of that circuit is mini-
mized. These circuits operate in low power mode where the power
consumed is measure in mW, µW, and nW (nano-watt) region and
still provide a useful and controlled circuit function operation.
ZERO TEMPERATURE COEFFICIENT (ZTC) OPERATION
For an EPAD MOSFET in this product family, operating points exist
where the various factors that cause the current to increase as a
function of temperature balance out those that cause the current to
decrease, thereby canceling each other, and resulting in a net tem-
perature coefficient of near zero. An example of this temperature
stable operating point is obtained by a ZTC voltage bias condition,
which is 0.38V above VGS(th) when VDS(ON) = +0.1V, resulting in
a temperature stable current level of about 380µA for the ALD2108xx
and 760µA for the ALD2129xx devices.
Performance characteristics of the EPAD MOSFET product family
are shown in the following graphs. In general, the gate threshold
voltage shift for each member of the product family causes other
affected electrical characteristics to shift linearly with VGS(th) bias
voltage. This linear shift in VGS causes the subthreshold I-V curves
to shift linearly as well. Accordingly, the subthreshold operating cur-
rent can be determined by calculating the gate source voltage drop
relative to its gate threshold voltage, VGS(th).
NORMALLY-ON FIXED RDS(ON) AT VGS = GROUND
Several members of this MOSFET family produce a fixed resis-
tance when their gate is grounded. For ALD210800, the drain cur-
rent at VDS = 0.1V is @ 10µA at VGS = 0.00V. Thus, just by ground-
ing the gate of the ALD210800, a resistor with RDS(ON) = ~10KΩ is
produced (For ALD212900 device, RDS(ON) = ~5KΩ). When an
ALD214804 gate is grounded, the drain current IDS = 424µA @
VDS = 0.1V, producing RDS(ON) = ~236Ω. Similarly, ALD214813
and ALD214835 produces 1.71mA and 3.33mA for each MOSFET,
respectively, at VGS = 0.00V, producing RDS(ON) values of 59Ω
and 30Ω, respectively. For example, when all 4 MOSFETs in an
ALD214835 are connected in parallel, an on-resistance of 30/4 =
~7.5Ω is measured between the Drain and Source terminals when
VGS = V- = 0.00V, producing a fixed on-resistance without any gate
bias voltages applied to the device.
One of the key performance benefits of using matched-pair EPAD
MOSFETs is to maintain temperature tracking between the differ-
ent devices in the same package. In general, for EPAD MOSFET
matched pair devices, one device of the matched pair has gate
leakage currents, junction temperature effects, and drain current
temperature coefficient as a function of bias voltage that cancel out
similar effects of the other device, resulting in a temperature stable
circuit. As mentioned earlier, this temperature stability can be fur-
ther enhanced by biasing the matched-pairs at Zero Tempco (ZTC)
point, even though that may require special circuit configurations
and power consumption design considerations.
POWER SUPPLY SEQUENCES AND ESD CONTROL
EPAD MOSFETs are robust and reliable, as demonstrated by more
than a decade of production history supplied to a large installed
base of customers across the world. However, these devices do
require a few design and handling precautions in order for them to
be used successfully.
EPAD MOSFETs, being a CMOS Integrated Circuit, in addition to
having Drain, Gate and Source pins normally found in a MOSFET
device, have three other types of pins, namely V+, V- and IC pins.
V+ is connected to the substrate, which must always be connected
to the most positive supply in a circuit. V- is the body of the MOSFET,
which must be connected to the most negative supply voltage in
the circuit. IC pins are internally connected pins, which must also
be connected to V-. Drain, Gate and Source pins must have volt-
ages between V- and V+ at all times.
Proper power-up sequencing requires powering up supply voltages
before applying any signals. During the power down cycle, remove
all signals before removing V- and V+. This way internally back
biased diodes are never allowed to become forward biased, possi-
bly causing damage to the device. Of course, standard ESD con-
trol procedures should also be observed so that static charge does
not degrade the performance of the devices.
Advanced Linear Devices
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