ALD212904 Datasheet PDF - Advanced Linear Devices

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ALD212904
Advanced Linear Devices

Part Number ALD212904
Description MOSFET
Page 12 Pages


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ADVANCED
LINEAR
DEVICES, INC.
PRECISION N-CHANNEL EPAD® MOSFET ARRAY
DUAL HIGH DRIVE NANOPOWER™ MATCHED PAIR
e TM
EPAD ®
ENAB
L
E
D
ALD212904
VGS(th)= +0.40V
GENERAL DESCRIPTION
The ALD212904 precision enhancement mode N-Channel EPAD® MOSFET
array is precision matched at the factory using ALD’s proven EPAD® CMOS
technology. These dual monolithic devices are enhanced additions to the
ALD110904 EPAD® MOSFET Family, with increased forward transconductance
and output conductance, particularly at very low supply voltages.
Intended for low voltage, low power small signal applications, the ALD212904
features precision +0.40V threshold voltage, which enables circuit designs with
input/output signals referenced to very low operating voltage ranges. With these
devices, a circuit with multiple cascading stages can be built to operate at ex-
tremely low supply/bias voltage levels. For example, a nanopower input ampli-
fier stage operating at less than 0.2V supply voltage has been successfully built
with these devices.
ALD212904 EPAD MOSFETs feature exceptional matched pair electrical char-
acteristics of Gate Threshold Voltage VGS(th) set precisely at +0.40V +0.020V,
IDS = +20µA @ VDS = 0.10V, with a typical offset voltage of only +0.002V (2mV).
Built on a single monolithic chip, they also exhibit excellent temperature track-
ing characteristics. These precision devices are versatile as design components
for a broad range of analog small signal applications such as basic building
blocks for current mirrors, matching circuits, current sources, differential ampli-
fier input stages, transmission gates, and multiplexers. They also excel in lim-
ited operating voltage applications, such as very low level voltage-clamps and
nano-power normally-on circuits.
In addition to precision matched-pair electrical characteristics, each individual
EPAD MOSFET also exhibits well controlled manufacturing characteristics, en-
abling the user to depend on tight design limits from different production batches.
These devices are built for minimum offset voltage and differential thermal re-
sponse, and they can be used for switching and amplifying applications in +0.1V
to +10V (+0.05V to +5V) powered systems where low input bias current, low
input capacitance, and fast switching speed are desired. At VGS > +0.40V, the
device exhibits enhancement mode characteristics whereas at VGS < +0.40V
the device operates in the subthreshold voltage region and exhibits conven-
tional sub threshold characteristics, with well controlled turn-off and sub-thresh-
old levels that operate the same as standard enhancement mode MOSFETs.
The ALD212904 features high input impedance (2.5 x 1010) and high DC cur-
rent gain (>108). A sample calculation of the DC current gain at a drain output
current of 30mA and input current of 300pA at 25°C is 30mA/300pA =
100,000,000, which translates into a dynamic operating current range of about
eight orders of magnitude. A series of four graphs titled “Forward Transfer Char-
acteristics”, with the 2nd and 3rd sub-titled “expanded (subthreshold)” and “fur-
ther expanded (subthreshold)”, and the 4th sub-titled “low voltage”, illustrates
the wide dynamic operating range of these devices.
Generally it is recommended that the V+ pin be connected to the most positive
voltage and the V- and IC (internally-connected) pins to the most negative volt-
age in the system. All other pins must have voltages within these voltage limits
at all times. Standard ESD protection facilities and handling procedures for static
sensitive devices are highly recommended when using these devices.
ORDERING INFORMATION (“L” suffix denotes lead-free (RoHS))
Operating Temperature Range *
0°C to +70°C
8-Pin SOIC Package
8-Pin Plastic Dip Package
ALD212904SAL
ALD212904PAL
*Contact factory for industrial temp. range or user-specified threshold voltage values.
FEATURES & BENEFITS
• Precision VGS(th) = +0.40V +0.020V
• VOS (VGS(th) match) 10mV max.
• Sub-threshold voltage (nano-power) operation
• < 400mV min. operating voltage
• < 1nA min. operating current
• < 1nW min. operating power
• > 100,000,000:1 operating current ranges
• High transconductance and output conductance
• Low RDS(ON) of 14
• Output current > 50mA
• Matched and tracked tempco
• Tight lot-to-lot parametric control
• Positive, zero, and negative VGS(th) tempco
• Low input capacitance and leakage currents
APPLICATIONS
• Low overhead current mirrors and current sources
• Zero Power Normally-On circuits
• Energy harvesting circuits
• Very low voltage analog and digital circuits
• Zero power fail-safe circuits
• Backup battery circuits & power failure detector
• Extremely low level voltage-clamps
• Extremely low level zero-crossing detector
• Matched source followers and buffers
• Precision current mirrors and current sources
• Matched capacitive probes and sensor interfaces
• Charge detectors and charge integrators
• High gain differential amplifier input stage
• Matched peak-detectors and level-shifters
• Multiple Channel Sample-and-Hold switches
• Precision Current multipliers
• Discrete matched analog switches/multiplexers
• Nanopower discrete voltage comparators
PIN CONFIGURATION
ALD212904
V-
IC* 1
V-
8 V+
GN1
DN1
S12
2
3
4
M1 M2
V-
7 GN2
6 DN2
5 V-
SAL, PAL PACKAGES
*IC pins are internally connected, connect to V-
©2014 Advanced Linear Devices, Inc., Vers. 1.1
www.aldinc.com
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ABSOLUTE MAXIMUM RATINGS
Drain-Source voltage, VDS
10.6V
Gate-Source voltage, VGS
10.6V
Operating Current
80mA
Power dissipation
500mW
Operating temperature range SAL, PAL
0°C to +70°C
Storage temperature range
-65°C to +150°C
Lead temperature, 10 seconds
+260°C
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
OPERATING ELECTRICAL CHARACTERISTICS
V+ = +5V V- = GND TA = 25°C unless otherwise specified
ALD212904
Parameter
Gate Threshold Voltage
Symbol
VGS(th)
Min
0.38
Typ
0.40
Offset Voltage
VOS
2
Offset Voltage Tempco
GateThreshold Voltage Tempco
TCVOS
TCVGS(th)
On Drain Current
Forward Transconductance
IDS(ON)
GFS
5
-1.7
0.0
+1.6
79
85
38
Transconductance Mismatch
Output Conductance
GFS
GOS
1.8
2.3
Drain Source On Resistance
RDS(ON)
14
Drain Source On Resistance
Drain Source On Resistance
Tolerance
RDS(ON)
RDS(ON)
5
1.18
1.8
Max
0.42
10
Unit Test Conditions
V IDS =20µA, VDS = 0.1V
mV VGS(th)M1 - VGS(th)M2
µV/°C VDS1 = VDS
mV/°C
mA
µA
mmho
ID = 20µA, VDS = 0.1V
ID = 760µA, VDS = 0.1V
ID = 1.5mA, VDS = 0.1V
VGS = +3.4V, VDS = +3V
VGS = +0.5V, VDS = +0.1V
VGS = +3.4V
VDS = +3.0V
%
mmho
VGS = +3.4V
VDS = +3.0V
VGS = +5.4V
VDS = +0.1V
KVGS = +0.4V, VDS = +0.1V
VGS = +0.5V, VDS = +0.1V
% VGS = +5.4V
VDS = +0.1V
Drain Source On Resistance
Mismatch
RDS(ON)
Drain Source Breakdown
Voltage
BVDSX
Drain Source Leakage Current1 IDS(OFF)
10
Gate Leakage Current1
IGSS
Input Capacitance
CISS
Transfer Reverse Capacitance CRSS
Turn-on Delay Time
Turn-off Delay Time
ton
toff
Crosstalk
Notes: 1 Consists of junction leakage currents
0.6
10
5
30
2
10
10
60
%
V V- = VGS = -0.6V
IDS = 10µA
400 pA VGS = -0.6V, VDS = +5V
V- = -5V
4 nA TA = 125°C
200 pA VGS = +5V, VDS = 0V
1 nA TA = 125°C
pF
pF
ns V+ = 5V, RL = 5K
V+ = 5V, RL = 5K
dB f = 100KHz
ALD212904
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PERFORMANCE CHARACTERISTICS OF EPAD®
PRECISION MATCHED PAIR MOSFET FAMILY
ALD2108xx/ALD2129xx/ALD2148xx/ALD2169xx high precision
monolithic quad/dual N-Channel MOSFET arrays are enhanced
versions of the ALD1108xx/ALD1109xx EPAD® MOSFET family, with
increased forward transconductance and output conductance, in-
tended for operation at very low power supply voltages. These de-
vices are also capable of sub-threshold operation with less than
1nA of operating supply currents and at the same time delivering
higher output drive currents (typ. > 50mA). They feature precision
Gate Offset Voltages, VOS , defined as the difference in VGS(th)
between MOSFET pairs M1 and M2 or M3 and M4.
ALD's Electrically Programmable Analog Device (EPAD®) technol-
ogy provides the industry's only family of matched MOSFET tran-
sistors with a range of precision gate-threshold voltage values. All
members of this family are designed and actively programmed for
exceptional matching of device electrical and temperature charac-
teristics. Gate Threshold Voltage VGS(th) values range from -3.50V
Depletion Mode to +3.50V Enhancement Mode devices, including
standard products with VGS(th) specified at -3.50V, -1.30V, -0.40V,
+0.00V, +0.20V, +0.40V, +0.80V, +1.40V, and +3.30V. ALD can
also provide any customer-desired VGS(th) between -3.50V and
+3.50V on a special order basis. For all these devices ALD EPAD
technology enables excellent well-controlled gate threshold volt-
age, subthreshold voltage, and low leakage characteristics. With
well matched design and precision programming, units from differ-
ent production lots provide the user with exceptional matching and
uniformity characteristics. Built on the same monolithic IC chip, the
units also have excellent temperature tracking characteristics.
This ALD2108xx/ALD2129xx/ALD2148xx/ALD2169xx EPAD
MOSFET Array product family (EPAD MOSFET) is available in three
separate categories, each providing a distinctly different set of elec-
trical specifications and characteristics. The first category is the
ALD210800A/ALD210800/ALD212900A/ALD212900 Zero-Thresh-
old™ mode EPAD MOSFETs. The second is the ALD2108xx/
ALD2129xx enhancement mode EPAD MOSFETs. The third cat-
egory includes the ALD2148xx/ALD2169xx depletion mode EPAD
MOSFETs. (The suffix “xx” denotes threshold voltage in 0.1V steps,
for example, xx=08 denotes 0.80V). For each device, there is a
zero-tempco bias current and bias voltage point. When a design
utilizes such a feature, then the gate-threshold voltage is tempera-
ture stable, greatly simplifying certain designs where stability of
certain circuit parameters over a temperature range is desired.
The ALD2148xx/ALD2169xx (quad/dual) features Depletion Mode
EPAD MOSFETs, which are normally-on devices at zero applied
gate voltage. The VGS(th) is set at a negative voltage level
(V- < VGS < VS) at which the EPAD MOSFET turns off. Without a
supply voltage and/or with VGS = V- = 0.00V = Ground, the EPAD
MOSFET device is already turned on and exhibits a defined and
controlled on-resistance RDS(ON). An EPAD MOSFET may be
turned off when a negative voltage is applied to V- pin and VGS set
more negative than its VGS(th). These Depletion Mode EPAD
MOSFETs are different from most other depletion mode MOSFETs
and JFETs in that they do not exhibit high gate leakage currents
and channel/junction leakage currents, while they stay controlled,
modulated and turned off at precise voltages. The same MOSFET
device equations as those for enhancement mode devices apply.
KEY APPLICATION ENVIRONMENTS
EPAD MOSFETs are ideal for circuits requiring low VOS and low
operating currents with tracked differential thermal responses. They
feature low input bias currents (less than 200pA max.), low input
capacitance and fast switching speed. These and other operating
characteristics offer unique solutions in one or more of the follow-
ing operating environments:
* Low supply voltage: 0.1V to 10V (+0.05V to +5V)
* Ultra low supply voltage: < +10mV to +0.1V
* Nanopower operation: voltage x current = nW or µW
* Precision VOS characteristics
* Matching and tracking of multiple MOSFETs
* Matching across multiple packages
ELECTRICAL CHARACTERISTICS
The turn-on and turn-off electrical characteristics of the EPAD
MOSFET products are shown in the IDS(ON) vs. VDS(ON) and
IDS(ON) vs. VGS graphs. Each graph shows IDS(ON) versus VDS(ON)
characteristics as a function of VGS in a different operating region
under different bias conditions, while IDS(ON) at a given gate input
voltage is controlled and predictable. A series of four graphs titled
“Forward Transfer Characteristics”, with the 2nd and 3rd sub-titled
“expanded (subthreshold)” and “further expanded (subthreshold)”,
and the 4th sub-titled “low voltage”, illustrates the wide dynamic
operating range of these devices.
The ALD210800A/ALD210800 are quad Zero Threshold MOSFETs
in which the individual gate-threshold voltage of each MOSFET is
set at zero, VGS(th) = 0.00V at IDS(ON) = 10µA @ VDS(ON) = +0.1V
(IDS(ON) = 20µA for the dual ALD212900A/ALD212900). Zero
Threshold MOSFETs operate in the enhancement region when op-
erated above threshold voltage (VGS > 0.00V and IDS > 10µA) and
subthreshold region when operated at or below threshold voltage
(VGS 0.00V and IDS < 10µA). These devices, along with other
low VGS(th) members of the product family, enable ultra low supply
voltage analog or digital operation and nanopower circuit designs,
thereby reducing or eliminating the use of very high valued (expen-
sive) resistors in many cases.
The ALD2108xx/ALD2129xx (quad/dual) product family features
precision matched enhancement mode EPAD MOSFET devices,
which require a positive gate bias voltage VGS to turn on. Precision
VGS(th) values at +3.30V, +1.40V, +0.80V, +0.40V and +0.20V are
offered. No conductive channel exists between the source and drain
at zero applied gate voltage (VGS = 0.00V) for +3.30V, +1.40V and
+0.80V versions. The +0.40V and the +0.20V versions have a sub-
threshold current at about 1nA and 100nA for the ALD2108xx (2nA
and 200nA for the ALD2129xx) respectively at zero applied gate
voltage. They are also capable of delivering lower RDS(ON) and
higher output currents greater than 68mA (see specifications).
Classic MOSFET equations for an N-channel MOSFET also apply
to EPAD MOSFETs.
The drain current in the linear region (VDS(ON) < VGS - VGS(th)) is
given by:
IDS(ON) = u . COX . W/L . [VGS - VGS(th) - VDS/2] . VDS(ON)
where:
u = Mobility
COX = Capacitance / unit area of Gate electrode
VGS = Gate to Source Voltage
VGS(th) = Gate Threshold (Turn-on)Voltage
VDS(ON) = Drain to Source On Voltage
W = Channel width
L = Channel length
In this region of operation the IDS(ON) value is proportional to the
VDS(ON) value and the device can be used as a gate-voltage con-
trolled resistor.
For higher values of VDS(ON) where VDS(ON) VGS - VGS(th), the
saturation current IDS(ON) is now given by (approx.):
IDS(ON) = u . COX . W/L . [VGS - VGS(th)]2
ALD212904
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PERFORMANCE CHARACTERISTICS OF EPAD®
PRECISION MATCHED PAIR MOSFET FAMILY (cont.)
SUB-THRESHOLD REGION OF OPERATION
PERFORMANCE CHARACTERISTICS
The gate threshold (turn-on) voltage VGS(th) of the EPAD MOSFET
is a voltage below which the MOSFET conduction channel rapidly
turns off. For analog designs, this gate threshold voltage directly
affects the operating signal voltage range and the operating bias
current levels.
At a voltage below VGS(th), an EPAD MOSFET exhibits a turn-off
characteristic in an operating region called the subthreshold re-
gion. This is when the EPAD MOSFET conduction channel rapidly
turns off as a function of decreasing applied gate voltage. The con-
duction channel, induced by the gate voltage on the gate elec-
trode, decreases exponentially and causes the drain current to de-
crease exponentially as well. However, the conduction channel does
not shut off abruptly with decreasing gate voltage, but rather de-
creases at a fixed rate of about 104mV per decade of drain current
decrease. For example, for the ALD2108xx device, if the gate thresh-
old voltage is +0.20V, the drain current is 10µA at VGS = +0.20V.
At VGS = +0.096V, the drain current would decrease to 1µA. Ex-
trapolating from this, the drain current is about 0.1µA at
VGS = 0.00V, 1nA at VGS = -0.216V, and so forth. This subthresh-
old characteristic extends all the way down to current levels below
1nA and is limited by junction leakage currents.
At a drain current of “zero current” as defined and selected by the
user, the VGS voltage at that zero current can now be estimated.
Note that using the above example, with VGS(th) = +0.20V, the
drain current still hovers around 100nA when the gate is at ground
voltage. With a device that has VGS(th) = +0.40V (part number
ALD210804), the drain current is about 2nA when the gate is at
ground potential. Thus, in this case an input signal referenced to
ground can operate with a natural drain current of only 2nA internal
bias current, dissipating nano-watts of power.
LOW POWER AND NANOPOWER
When supply voltages decrease, the power consumption of a given
load resistor decreases as the square of the supply voltage. Thus,
one of the benefits in reducing supply voltage is to reduce power
consumption. While decreasing power supply voltages and power
consumption go hand-in-hand with decreasing useful AC bandwidth
and increased noise effects in the circuit, a circuit designer can
make the necessary tradeoffs and adjustments in any given circuit
design and bias the circuit accordingly for optimal performance.
With EPAD MOSFETs, a circuit that performs any specific function
can be designed so that power consumption of that circuit is mini-
mized. These circuits operate in low power mode where the power
consumed is measure in mW, µW, and nW (nano-watt) region and
still provide a useful and controlled circuit function operation.
ZERO TEMPERATURE COEFFICIENT (ZTC) OPERATION
For an EPAD MOSFET in this product family, operating points exist
where the various factors that cause the current to increase as a
function of temperature balance out those that cause the current to
decrease, thereby canceling each other, and resulting in a net tem-
perature coefficient of near zero. An example of this temperature
stable operating point is obtained by a ZTC voltage bias condition,
which is 0.38V above VGS(th) when VDS(ON) = +0.1V, resulting in
a temperature stable current level of about 380µA for the ALD2108xx
and 760µA for the ALD2129xx devices.
Performance characteristics of the EPAD MOSFET product family
are shown in the following graphs. In general, the gate threshold
voltage shift for each member of the product family causes other
affected electrical characteristics to shift linearly with VGS(th) bias
voltage. This linear shift in VGS causes the subthreshold I-V curves
to shift linearly as well. Accordingly, the subthreshold operating cur-
rent can be determined by calculating the gate source voltage drop
relative to its gate threshold voltage, VGS(th).
NORMALLY-ON FIXED RDS(ON) AT VGS = GROUND
Several members of this MOSFET family produce a fixed resis-
tance when their gate is grounded. For ALD210800, the drain cur-
rent at VDS = 0.1V is @ 10µA at VGS = 0.00V. Thus, just by ground-
ing the gate of the ALD210800, a resistor with RDS(ON) = ~10Kis
produced (For ALD212900 device, RDS(ON) = ~5K). When an
ALD214804 gate is grounded, the drain current IDS = 424µA @
VDS = 0.1V, producing RDS(ON) = ~236. Similarly, ALD214813
and ALD214835 produces 1.71mA and 3.33mA for each MOSFET,
respectively, at VGS = 0.00V, producing RDS(ON) values of 59
and 30, respectively. For example, when all 4 MOSFETs in an
ALD214835 are connected in parallel, an on-resistance of 30/4 =
~7.5is measured between the Drain and Source terminals when
VGS = V- = 0.00V, producing a fixed on-resistance without any gate
bias voltages applied to the device.
MATCHING CHARACTERISTICS
One of the key performance benefits of using matched-pair EPAD
MOSFETs is to maintain temperature tracking between the differ-
ent devices in the same package. In general, for EPAD MOSFET
matched pair devices, one device of the matched pair has gate
leakage currents, junction temperature effects, and drain current
temperature coefficient as a function of bias voltage that cancel
out similar effects of the other device, resulting in a temperature
stable circuit. As mentioned earlier, this temperature stability can
be further enhanced by biasing the matched-pairs at Zero Tempco
(ZTC) point, even though that may require special circuit configu-
rations and power consumption design considerations.
POWER SUPPLY SEQUENCES AND ESD CONTROL
EPAD MOSFETs are robust and reliable, as demonstrated by more
than a decade of production history supplied to a large installed
base of customers across the world. However, these devices do
require a few design and handling precautions in order for them to
be used successfully.
EPAD MOSFETs, being a CMOS Integrated Circuit, in addition to
having Drain, Gate and Source pins normally found in a MOSFET
device, have three other types of pins, namely V+, V- and IC pins.
V+ is connected to the substrate, which must always be connected
to the most positive supply in a circuit. V- is the body of the MOSFET,
which must be connected to the most negative supply voltage in
the circuit. IC pins are internally connected pins, which must also
be connected to V-. Drain, Gate and Source pins must have volt-
ages between V- and V+ at all times.
Proper power-up sequencing requires powering up supply voltages
before applying any signals. During the power down cycle, remove
all signals before removing V- and V+. This way internally back
biased diodes are never allowed to become forward biased, possi-
bly causing damage to the device. Of course, standard ESD con-
trol procedures should also be observed so that static charge does
not degrade the performance of the devices.
ALD212904
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