AK7719 Datasheet PDF - AKM

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AK7719
AKM

Part Number AK7719
Description Low Power DSP
Page 16 Pages


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[AK7719]
AK7719
Low Power DSP for Voice and Audio Processing
GENERAL DESCRIPTION
The AK7719 is a highly integrated digital signal processor (DSP) with four digital interface ports. AKM’s
DSP core is optimized for both narrowband and wideband voice processing, as well as full bandwidth
digital audio processing. An integrated clock generator for the DSP master clock eliminates the need for
external clocks. The RAM-based DSP can be programmed for user requirements. The AK7719 is housed
in a 25-pin CSP package. It is a very low power device, suitable for mobile applications.
FEATURES
Embedded DSP
- Flexible programming with built-in program and data memories
- Hardware accelerator
- Word length: 24-bits (Data RAM 24-bit floating point)
- Multiplier 20 x 20 Æ 40-bits (double precision available)
- Divider 20 / 20 Æ 20-bits
- ALU: 44-bit arithmetic operation (with 4-bit overflow margin)
24-bit floating point arithmetic and logic operation
- Program RAM: 4096w x 36-bits
- Coefficient RAM: 2048w x 20-bits
- Data RAM: 2048w x 24-bits (24-bit floating point)
- Offset Register: 32w x 15-bits
- Delay RAM: 16384w x 24-bits(24-bit floating point)
- 5625 steps at 16kHz sampling rate, 1875 steps at 48kHz sampling rate
- Internal clock generator
Audio Interface Format
- 24-bit Left justified, I2S,
- 16/24bit linear, 8-bit A-law, 8-bit µ-law PCM
- Sampling rate 8kHz ~ 48kHz
- Up/Down Sampling rate converter for Port#2 (8kHz 16kHz)
μC I/F: I2C-Compatible, SPI
Operational, Sleep, Power down
Power Supply
VDD (DSP Core): 1.2V ±0.1V
TVDD (PCM I/F): 1.6V ~ 3.6V
Operating Temperature Range: -20°C ~ 85°C
Package: 25-Pin WL-CSP (2.62mm x2.93mm, 0.5mm pitch)
Power Consumption: 6.2mA (7.5mW) typ. (Narrowband Hands Free mode operation)
MS1351-E-00-PB
1
2012/01
Free Datasheet http://www.datasheet4u.com/



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Block Diagram
PDN
VSS
TVDD VDD
SYNC1
BCLK1
SDIN1
SDOUT1
SYNC3/JX1
BCLK3/JX0
SDIN3
SDOUT3/GP0
PCM
Interface1
(Port#1)
PCM
Interface3
(Port#3)
CGU
(CLK
Gen
Unit)
DIN1
AKM
DSP
Core
DOUT2
DOUT1
DIN2
DOUT4/GP1
JX1
JX0
DIN3
DIN4
WDT/CRC
DOUT3/GP0
DSPCLK
Memory
PCM
Interface2
(Port#2)
PCM
Interface4
(Port#4)
RDY
Control
Interface
Figure 1. Block Diagram
[AK7719]
TEST
SYNC2
BCLK2
SDOUT2
SDIN2
SDOUT4/GP1
SDIN4
STO/RDY
I2C
SCLK/CAD0
SI/CAD1
CSN/SCL
SO/SDA
MS1351-E-00-PB
2
2012/01
Free Datasheet http://www.datasheet4u.com/



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[AK7719]
Ordering Guide
AK7719ECB -20 +85°C 25-pin CSP (0.5mm pitch) Black type
AKD7719
Evaluation board for AK7719
Pin Layout
Top View
A BCD E
5
4
3
INDEX
2 MARK
1
5
4
Bottom View
3
2
1
E DC B A
5 PDN SDIN1 SDOUT1 BCLK1 SYNC1
4
VDD
BCLK3/
JX0
SDIN3
SDOUT3/
GP0
SYNC2
3
VSS
SYNC3/
JX1
TEST
STO/
RDY
BCLK2
2
TVDD
I2C
SDIN4
SDOU4/
GP1
SDIN2
1
SI/CAD1
SCLK/
CAD0
CSN/
SCL
SO/ SDA SDOUT2
ABCDE
TOP View
MS1351-E-00-PB
3
2012/01
Free Datasheet http://www.datasheet4u.com/



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[AK7719]
PIN/FUNCTION
NO Pin Name I/O
Function
A4 VDD
- Core Power Supply Pin 1.2V
A2 TVDD
A3 VSS
- I/O power Supply Pin 1.63.6V
- Ground Pin 0V
A5 PDN
P Power-Down Mode Pin
I “H”: Power-up, “L”: Power-down, reset the control register.
The AK7719 must be reset once upon power-up.
D3 STO
RDY
O
Status Output Pin (Active High)
Data Write Ready output pin for control I/F
(STRDY bit = “0”)
(STRDY bit = “1”)
E5 SYNC1
I Frame Sync 1 pin
D5 BCLK1
I
Serial Data Clock 1 Pin
AK7719 goes into standby state when BCLK1 is not present.
B5 SDIN1
I Serial Data Input 1 Pin
C5 SDOUT1
O Serial Data Output 1 Pin
E4 SYNC2
O Frame Sync 1 pin
E3 BCLK2
O Serial Data Clock 2 Pin
E2 SDIN2
I Serial Data Input 2 Pin
E1 SDOUT2
O Serial Data Output 2 Pin
B3
SYNC3
JX1
I
Frame Sync 3 pin
Conditional Jump 1 Pin
(SELPT bit = “1”)
(SELPT bit = “0”)
B4
BCLK3
JX0
C4 SDIN3
I
Serial Data Clock 3 Pin
Conditional Jump 0 Pin
I Serial Data Input 3 Pin
(SELPT bit = “1”)
(SELPT bit = “0”)
D4
SDOUT3
GP0
O
Serial Data Output 3 Pin
DSP Programmable output 0 Pin
(SELDO3 bit = “0”)
(SELDO3 bit = “1”)
C2 SDIN4
I Serial Data Input 4 Pin
D2
SDOUT4
GP1
B2 I2C
O
Serial Data Output 4 Pin
DSP Programmable output 1 Pin
I Control Interface Mode Select Pin
(SELDO4 bit = “0”)
(SELDO4 bit = “1”)
“H”: I2C, “L”: SPI
B1
SCLK
CAD0
C1
CSN
SCL
D1
SO
SDA
I
Serial Clock Input pin
Slave Address 0 Input pin
I
Chip select pin
Control Interface clock input pin
O Serial data output pin
I/O Control Interface input/output acknowledge pin
SPI (I2C pin = “L”)
I2C (I2C pin = “H”)
SPI (I2C pin = “L”)
I2C (I2C pin = “H”)
SPI (I2C pin = “L”)
I2C (I2C pin = “H”)
A1
SI
CAD1
I
Serial data input pin
Slave Address 1 Input pin
SPI (I2C pin = “L”)
I2C(I2C pin = “H”)
C3 TEST
I Test pin (pull-down resistor) must be connected to VSS.
Note 1. All input pins must not be allowed to float.
Note 2. I2C and CAD0/1 pins must be fixed to “L” (VSS) or “H” (TVDD).
MS1351-E-00-PB
4
2012/01
Free Datasheet http://www.datasheet4u.com/



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