ADSP-BF547 Datasheet PDF - Analog Devices

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ADSP-BF547
Analog Devices

Part Number ADSP-BF547
Description High Performance Convergent Multimedia Blackfin Processor
Page 30 Pages


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Embedded Processor
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
FEATURES
Up to 600 MHz high-performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs
RISC-like register and instruction model
Wide range of operating voltages and flexible booting
options
Programmable on-chip voltage regulator
400-ball CSP_BGA, RoHS compliant package
MEMORY
Up to 324K bytes of on-chip memory comprised of
instruction SRAM/cache; dedicated instruction SRAM; data
SRAM/cache; dedicated data SRAM; scratchpad SRAM
External sync memory controller supporting either DDR
SDRAM or mobile DDR SDRAM
External async memory controller supporting 8-/16-bit async
memories and burst flash devices
NAND flash controller
4 memory-to-memory DMA pairs, 2 with ext. requests
Memory management unit providing memory protection
Code security with Lockbox® secure technology and 128-bit
AES/ ARC4 data encryption
One-time-programmable (OTP) memory
PERIPHERALS
High-speed USB On-the-Go (OTG) with integrated PHY
SD/SDIO controller
ATA/ATAPI-6 controller
Up to 4 synchronous serial ports (SPORTs)
Up to 3 serial peripheral interfaces (SPI-compatible)
Up to 4 UARTs, two with automatic H/W flow control
Up to 2 CAN (controller area network) 2.0B interfaces
Up to 2 TWI (2-wire interface) controllers
8- or 16-bit asynchronous host DMA interface
Multiple enhanced parallel peripheral interfaces (EPPIs),
supporting ITU-R BT.656 video formats and 18-/24-bit LCD
connections
Media transceiver (MXVR) for connection to a MOST network
Pixel compositor for overlays, alpha blending, and color
conversion
Up to eleven 32-bit timers/counters with PWM support
Real-time clock (RTC) and watchdog timer
Up/down counter with support for rotary encoder
Up to 152 general-purpose I/O (GPIOs)
On-chip PLL capable of 0.5× to 64× frequency multiplication
Debug/JTAG interface
CAN (0-1)
TWI (0-1)
TIMERS(0-10)
COUNTER
KEYPAD
PAB 16
VOLTAGE
REGULATOR
JTAG TEST AND
EMULATION
RTC
B
WATCHDOG
TIMER
OTP
INTERRUPTS
L2
SRAM
L1
INSTR ROM
L1
INSTR SRAM
L1
DATA SRAM
MXVR
USB
DCB 32
EAB 64
DEB 32
BOOT
ROM
EXTERNAL PORT
NOR, DDR, MDDR
DDR/MDDR
16
ASYNC
16
32-BIT DMA
16-BIT DMA
DAB1 32
DAB0 16
ATAPI
NAND FLASH
CONTROLLER
HOST DMA
UART (0-1)
UART (2-3)
SPI (0-1)
SPI (2)
SPORT (2-3)
SPORT (0-1)
SD / SDIO
EPPI (0-2)
PIXEL
COMPOSITOR
Figure 1. ADSP-BF549 Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/461-3113 © 2009 Analog Devices, Inc. All rights reserved.



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TABLE OF CONTENTS
General Description ................................................. 3
Low Power Architecture ......................................... 4
System Integration ................................................ 4
Blackfin Processor Peripherals ................................. 4
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 6
DMA Controllers ................................................ 10
Real-Time Clock ................................................. 11
Watchdog Timer ................................................ 12
Timers ............................................................. 12
Up/Down Counter and Thumbwheel Interface .......... 12
Serial Ports (SPORTs) .......................................... 12
Serial Peripheral Interface (SPI) Ports ...................... 13
UART Ports (UARTs) .......................................... 13
Controller Area Network (CAN) ............................ 13
TWI Controller Interface ...................................... 14
Ports ................................................................ 14
Pixel Compositor (PIXC) ...................................... 14
Enhanced Parallel Peripheral Interface (EPPI) ........... 14
USB On-the-Go Dual-Role Device Controller ............ 15
ATA/ATAPI–6 Interface ...................................... 15
Keypad Interface ................................................. 15
Secure Digital (SD)/SDIO Controller ....................... 16
Code Security .................................................... 16
Media Transceiver MAC Layer (MXVR) .................. 16
Dynamic Power Management ................................ 17
Voltage Regulation .............................................. 18
Clock Signals ..................................................... 19
Booting Modes ................................................... 20
Instruction Set Description ................................... 23
Development Tools ............................................. 23
Designing an Emulator-Compatible Processor Board .. 24
MXVR Board Layout Guidelines ............................ 24
Pin Descriptions .................................................... 25
Specifications ........................................................ 34
Operating Conditions .......................................... 34
Electrical Characteristics ....................................... 36
Absolute Maximum Ratings ................................... 40
Timing Specifications ........................................... 41
Clock and Reset Timing ..................................... 41
Asynchronous Memory Read Cycle Timing ............ 43
Asynchronous Memory Write Cycle Timing ........... 45
DDR SDRAM/Mobile DDR SDRAM Clock and Control
Cycle Timing ............................................... 47
DDR SDRAM/Mobile DDR SDRAM Timing .......... 48
DDR SDRAM/Mobile DDR SDRAM Write Cycle
Timing ....................................................... 50
External Port Bus Request and Grant Cycle Timing .. 51
NAND Flash Controller Interface Timing .............. 53
Synchronous Burst AC Timing ............................ 57
External DMA Request Timing ............................ 58
Enhanced Parallel Peripheral Interface Timing ........ 59
Serial Ports Timing ........................................... 62
Serial Peripheral Interface (SPI) Port—Master
Timing ....................................................... 66
Serial Peripheral Interface (SPI) Port—Slave
Timing ....................................................... 67
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing ..... 68
General-Purpose Port Timing ............................. 69
Timer Cycle Timing .......................................... 70
Up/Down Counter/Rotary Encoder Timing ............ 71
SD/SDIO Controller Timing ............................... 72
MXVR Timing ................................................ 74
HOSTDP A/C Timing-Host Read Cycle ................ 75
HOSTDP A/C Timing-Host Write Cycle ............... 76
ATA/ATAPI-6 Interface Timing .......................... 77
USB On-The-Go-Dual-Role Device Controller
Timing ....................................................... 95
JTAG Test And Emulation Port Timing ................. 95
Output Drive Currents ......................................... 97
Thermal Characteristics ...................................... 103
400-Ball CSP_BGA Package .................................... 104
Outline Dimensions .............................................. 110
Automotive Products ............................................ 111
Ordering Guide ................................................... 111
REVISION HISTORY
2/09—Rev.A to Rev. B: Add 400 MHz and 600 MHz
specifications and mobile DDR.
Rev. B | Page 2 of 112 | February 2009



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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BFw5w4w8./DAaDt aSSPh-eBeFt 45U4. c9o m
GENERAL DESCRIPTION
The ADSP-BF54x Blackfin® processors are members of the
Blackfin family of products, incorporating the Analog
Devices/Intel Micro Signal Architecture (MSA). Blackfin pro-
cessors combine a dual-MAC state-of-the-art signal processing
engine, the advantages of a clean, orthogonal RISC-like micro-
processor instruction set, and single-instruction, multiple-data
(SIMD) multimedia capabilities into a single instruction-set
architecture.
Specific performance, memory configurations, and features of
ADSP-BF54x Blackfin processors are shown in Table 1.
Table 1. ADSP-BF54x Processor Features
Processor
Features
Lockbox® 1code security
11111
128-bit AES/ ARC4 data encryption
SD/SDIO controller
111–1
Pixel compositor
11111
18- or 24-bit EPPI0 with LCD
1111–
16-bit EPPI1, 8-bit EPPI2
11111
Host DMA port
1111–
NAND flash controller
11111
ATAPI
111–1
High-Speed USB OTG
111–1
Keypad interface
111–1
MXVR
1––––
CAN ports
22–21
TWI ports
22221
SPI ports
33322
UART ports
44433
SPORTs
44433
Up/Down counter
11111
Timers
11 11 11 11 8
General-Purpose I/O pins
152 152 152 152 152
Memory L1 Instruction SRAM/Cache 16 16 16 16 16
Configura- L1 Instruction SRAM
tions
(K Bytes)
L1 Data SRAM/Cache
L1 Data SRAM
48 48 48 48 48
32 32 32 32 32
32 32 32 32 32
L1 Scratchpad SRAM
L1 ROM2
44444
64 64 64 64 64
L2
L3 Boot ROM2
128 128 128 64 –
44444
Maximum Core Instruction Rate (MHz) 533 533 600 533 600
1 Lockbox is a registered trademark of Analog Devices, Inc.
2 This ROM is not customer-configurable.
Specific peripherals for ADSP-BF54x Blackfin processors are
shown in Table 2.
Table 2. Specific Peripherals for ADSP-BF54x Processors
Module
EBIU (async)
NAND flash controller
ATAPI
Host DMA port (HOSTDP)
SD/SDIO controller
EPPI0
EPPI1
EPPI2
SPORT0
SPORT1
SPORT2
SPORT3
SPI0
SPI1
SPI2
UART0
UART1
UART2
UART3
High-Speed USB OTG
CAN0
CAN1
TWI0
TWI1
Timer 0–7
Timer 8–10
Up/Down counter
Keypad interface
MXVR
GPIOs
PPPPP
PPPPP
PPP–P
PPPP–
PPP–P
PPPP–
PPPPP
PPPPP
PPP––
PPPPP
PPPPP
PPPPP
PPPPP
PPPPP
PPP––
PPPPP
PPPPP
PPP––
PPPPP
PPP–P
PP–PP
PP–P–
PPPPP
PPPP–
PPPPP
PPPP–
PPPPP
PPP–P
P––––
PPPPP
Rev. B | Page 3 of 112 | February 2009



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The ADSP-BF54x Blackfin processors are completely code- and
pin-compatible. They differ only with respect to their perfor-
mance, on-chip memory, and selection of I/O peripherals.
Specific performance, memory, and feature configurations are
shown in Table 1.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature on-chip
dynamic power management, the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. Reducing both voltage and frequency can result
in a substantial reduction in power consumption as compared
to reducing only the frequency of operation. This translates into
longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF54x Blackfin processors are highly integrated
system-on-a-chip solutions for the next generation of embed-
ded network connected applications. By combining industry-
standard interfaces with a high-performance signal processing
core, users can develop cost-effective solutions quickly without
the need for costly external components. The system peripherals
include a high-speed USB OTG (On-the-Go) controller with
integrated PHY, CAN 2.0B controllers, TWI controllers, UART
ports, SPI ports, serial ports (SPORTs), ATAPI controller,
SD/SDIO controller, a real-time clock, a watchdog timer, LCD
controller, and multiple enhanced parallel peripheral interfaces.
BLACKFIN PROCESSOR PERIPHERALS
The ADSP-BF54x processors contain a rich set of peripherals
connected to the core via several high bandwidth buses, provid-
ing flexibility in system configuration as well as excellent overall
system performance (see Figure 1 on Page 1). The general-
purpose peripherals include functions such as UARTs, SPI,
TWI, timers with pulse width modulation (PWM) and pulse
measurement capability, general-purpose I/O pins, a real-time
clock, and a watchdog timer. This set of functions satisfies a
wide variety of typical system support needs and is augmented
by the system expansion capabilities of the part. The ADSP-
BF54x processors contain dedicated network communication
modules and high-speed serial and parallel ports, an interrupt
controller for flexible management of interrupts from the on-
chip peripherals or external sources, and power management
control functions to tailor the performance and power charac-
teristics of the processor and system to many application
scenarios.
All of the peripherals, except for general-purpose I/O, CAN,
TWI, real-time clock, and timers, are supported by a flexible
DMA structure. There are also separate memory DMA channels
dedicated to data transfers between the processor's various
memory spaces, including external DDR (either standard or
mobile, depending on the device) and asynchronous memory.
Multiple on-chip buses running at up to 133 MHz provide
enough bandwidth to keep the processor core running along
with activity on all of the on-chip and external peripherals.
The ADSP-BF54x Blackfin processors include an on-chip volt-
age regulator in support of the dynamic power management
capability. The voltage regulator provides a range of core volt-
age levels when supplied from VDDEXT. The voltage regulator can
be bypassed at the user’s discretion.
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 5, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16- or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
Rev. B | Page 4 of 112 | February 2009



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