ADRF6820 Datasheet PDF - Analog Devices


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ADRF6820
Analog Devices

Part Number ADRF6820
Description Quadrature Demodulator
Page 30 Pages

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Data Sheet
695 MHz to 2700 MHz, Quadrature Demodulator
with Integrated Fractional-N PLL and VCO
ADRF6820
FEATURES
I/Q demodulator with integrated fractional-N PLL
RF input frequency range: 695 MHz to 2700 MHz
Internal LO frequency range: 356.25 MHz to 2850 MHz
Input P1dB: 14.5 dBm at 1900 MHz RF
Input IP3: 37 dBm at 1900 MHz RF
Programmable HD3/IP3 trim
Single pole, double throw (SPDT) RF input switch
RF digital step attenuation range: 0 dB to 15 dB
Integrated RF tunable balun for single-ended 50 Ω input
Multicore integrated VCO
Demodulated 1 dB bandwidth: 600 MHz
4 selectable baseband gain and bandwidth modes
Digital programmable LO phase offset and dc nulling
Programmable via 3-wire serial port interface (SPI)
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Cellular W-CDMA/GSM/LTE
Digital predistortion (DPD) receivers
Microwave point-to-point radios
FUNCTIONAL BLOCK DIAGRAM
RFIN0 29
15 14 13
SERIAL PORT
INTERFACE
RFIN1 22
2 3 8 9 23 25 26 28 38
DC/PHASE
CORRECTION
4 I+
5 I–
POLYPHASE
FILTER
QUAD
DIVIDER
35 LOIN+
34 LOIN–
PLL 39 REFIN
LDO
2.5V
LDO
VCO
1 19 30 36 31
VPOS_3P3
DC/PHASE
CORRECTION
27 33 40 10
DECL1 TO
DECL4
Figure 1.
11 21
VPOS_5V
6 Q–
7 Q+
GENERAL DESCRIPTION
The ADRF6820 is a highly integrated demodulator and synthesizer
ideally suited for next generation communication systems. The
feature rich device consists of a high linearity broadband I/Q
demodulator, an integrated fractional-N phase-locked loop (PLL),
and a low phase noise multicore, voltage controlled oscillator
(VCO). The ADRF6820 also integrates a 2:1 RF switch, an on-chip
tunable RF balun, a programmable RF attenuator, and two low
dropout (LDO) regulators. This highly integrated device fits
within a small 6 mm × 6 mm footprint.
The high isolation 2:1 RF switch and on-chip tunable RF balun
enable the ADRF6820 to support two single-ended, 50 Ω
terminated RF inputs. A programmable attenuator ensures
an optimal differential RF input level to the high linearity
demodulator core. The integrated attenuator offers an
attenuation range of 0 dB to 15 dB with a step size of 1 dB.
The ADRF6820 offers two alternatives for generating the
differential local oscillator (LO) input signal: externally via a
high frequency, low phase noise LO signal or internally via the
on-chip fractional-N synthesizer. The integrated synthesizer
enables continuous LO coverage from 356.25 MHz to 2850 MHz.
The PLL reference input can support a wide frequency range
because the divide or multiplication blocks can increase or
decrease the reference frequency to the desired value before it
is passed to the phase frequency detector (PFD).
When selected, the output of the internal fractional-N synthesizer
is applied to a divide-by-2 quadrature phase splitter. From the
external LO path, a 1× LO signal can be applied to the built-in
polyphase filter, or a 2× LO signal can be used with the divide-
by-2 quadrature phase splitter to generate the quadrature LO
inputs to the mixers.
The ADRF6820 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP package with an exposed paddle.
Performance is specified over the −40°C to +85°C temperature
range.
Rev. 0
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
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ADRF6820
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
System Specifications ................................................................... 3
Dynamic Performance................................................................. 3
Synthesizer/PLL Specifications................................................... 5
Digital Logic Specifications......................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 14
RF Input Switch .......................................................................... 14
Tunable Balun ............................................................................. 14
REVISION HISTORY
12/13—Revision 0: Initial Version
Data Sheet
RF Attenuator ............................................................................. 15
LO Generation Block ................................................................. 15
Active Mixers .............................................................................. 17
Baseband Buffers ........................................................................ 17
Serial Port Interface (SPI) ......................................................... 17
Applications Information .............................................................. 18
Basic Connections...................................................................... 18
RF Balun Insertion Loss Optimization ................................... 20
Bandwidth Select Modes ........................................................... 22
IP3 and Noise Figure Optimization......................................... 24
I/Q Output Loading ................................................................... 26
Image Rejection .......................................................................... 27
I/Q Polarity.................................................................................. 28
Layout .......................................................................................... 29
Register Map ................................................................................... 30
Register Address Descriptions.................................................. 31
Outline Dimensions ....................................................................... 44
Ordering Guide .......................................................................... 44
Rev. 0 | Page 2 of 44
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Data Sheet
ADRF6820
SPECIFICATIONS
SYSTEM SPECIFICATIONS
VPOS_5V = 5 V, VPOS_3P3 = 3.3 V, ambient temperature (TA) = 25°C, high-side LO injection, internal LO mode, RF attenuation range =
0 dB, input IP2/input IP3 tone spacing = 5 MHz and −5 dBm per tone, fIF = 40 MHz for BWSEL = 0 and fIF = 200 MHz for BWSEL = 2.
Table 1.
Parameter
RF INPUT
RF Frequency Range
Return Loss
Input Impedance
Input Power
LO INTERNAL FREQUENCY
LO Internal Frequency Range
External LO Frequency Range
LO Input Level
LO Input Impedance
SUPPLY VOLTAGE
VPOS_3P3
VPOS_5V
RF ATTENUATION RANGE
IF OUTPUTS
Gain Flatness
Quadrature Phase Error
I/Q Amplitude Imbalance
Output DC Offset
Output Common Mode
I/Q Output Impedance
TOTAL POWER CONSUMPTION
Test Conditions/Comments
Step size = 1 dB
Across any 20 MHz bandwidth
No correction applied
No correction applied
No correction applied
Differential
External LO, polyphase filter LO path
Internal PLL/VCO, 2× LO path
Min
695
356.25
350
−6
3.1
4.7
0
1.5
Typ
15
50
50
3.3
5.0
0.2
1
0.1
20
50
1100
1400
Max
2700
18
2850
6000
+6
3.5
5.25
15
2.4
Unit
MHz
MHz
dB
Ω
dBm
MHz
MHz
MHz
dBm
Ω
V
V
V
dB
dB
Degrees
dB
mV
V
Ω
mW
mW
DYNAMIC PERFORMANCE
Table 2.
Parameter
DEMODULATION BANDWIDTH
fRF = 900 MHz
Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation2
Test Conditions/Comments
1 dB bandwidth, fLO = 2100 MHz
3 dB bandwidth, fLO = 2100 MHz
Voltage gain
Internal LO
External LO
With respect to −5 dBm RF input power
With respect to −5 dBm RF input power
Isolation between RFIN0 to RFIN1
Isolation between RFIN1 to RFIN0
BWSEL01
Min Typ Max
240
480
BWSEL21
Min Typ Max
600
1400
Unit
MHz
MHz
+3.5
11
33
75
17
16
−82
−67
−78.5
−49
−55
−55
−2.5
14
37
72
19
18.5
−82
−67
−78.5
−49
−55
−55
dB
dBm
dBm
dBm
dB
dB
dBm
dBm
dBc
dBc
dBc
dBc
Rev. 0 | Page 3 of 44
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ADRF6820
Data Sheet
Parameter
fRF = 1900 MHz
Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation2
fRF = 2100 MHz
Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation2
fRF = 2650 MHz
Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation2
Test Conditions/Comments
Voltage gain
Internal LO
External LO
With respect to −5 dBm RF input power
With respect to −5 dBm RF input power
Isolation between RFIN0 to RFIN1
Isolation between RFIN1 to RFIN0
Voltage gain
Internal LO
External LO
With respect to −5 dBm RF input power
With respect to −5 dBm RF input power
Isolation between RFIN0 to RFIN1
Isolation between RFIN1 to RFIN0
Voltage gain
Internal LO
External LO
With respect to −5 dBm RF input power
With respect to −5 dBm RF input power
Isolation between RFIN0 to RFIN1
Isolation between RFIN1 to RFIN0
BWSEL01
BWSEL21
Min Typ Max Min Typ Max Unit
+3
12
37
72
18
17.5
−75
−64
−64.5
−43.5
−51
−39
−3
14.5
37
68
20
19.5
−75
−64
−64.5
−43.5
−51
−39
dB
dBm
dBm
dBm
dB
dB
dBm
dBm
dBc
dBc
dBc
dBc
+2.5
12
36
71
18
18
−72.5
−62
−71
−45
−48.5
−36.5
−3
15.5
37
70
20.5
20
−72.5
−62
−71
−45
−48.5
−36.5
dB
dBm
dBm
dBm
dB
dB
dBm
dBm
dBc
dBc
dBc
dBc
+1.5
13
36
71
19.5
19.5
−70
−57
−76
−46
−40.5
−33
−4
16.5
36
68
22
21.5
−70
−57
−76
−46
−40.5
−33
dB
dBm
dBm
dBm
dB
dB
dBm
dBm
dBc
dBc
dBc
dBc
1 See Table 15.
2 This is the isolation between the RF inputs. An input signal was applied to RFIN0, while RFIN1 was terminated with 50 Ω. The IF signal amplitude was measured at the
baseband output. Next, the internal switch was configured for RFIN1, and the feedthrough was measured as a delta from the fundamental. This difference is recorded
as isolation between RFIN0 and RFIN1.
Rev. 0 | Page 4 of 44
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