ADG1212-EP Datasheet PDF - Analog Devices

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ADG1212-EP
Analog Devices

Part Number ADG1212-EP
Description iCMOS Quad SPST Switches
Page 12 Pages


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Enhanced Product
Low Capacitance, Low Charge Injection,
±15 V/+12 V iCMOS Quad SPST Switches
ADG1212-EP
FEATURES
1 pF off capacitance
2.6 pF on capacitance
<1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V, +12 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP
Typical power consumption: <0.03 μW
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC
standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
GENERAL DESCRIPTION
The ADG1212-EP is a monolithic complementary metal-oxide
semiconductor (CMOS) device containing four independently
selectable switches designed on an iCMOS® (industrial CMOS)
process. iCMOS is a modular manufacturing process combining
high voltage CMOS and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no previous generation
of high voltage parts has been able to achieve. Unlike analog
ICs using conventional CMOS processes, iCMOS components
can tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
FUNCTIONAL BLOCK DIAGRAM
S1
IN1
D1
S2
IN2
ADG1212-EP D2
S3
IN3
D3
S4
IN4
D4
NOTES
1. SWITCHES SHOWN ARE
FOR LOGIC 1 INPUT.
Figure 1.
The ultralow capacitance and charge injection of this switch
makes it an ideal solution for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth makes
the part suitable for video signal switching.
iCMOS construction ensures ultralow power dissipation, making
the part ideally suited for portable and battery-powered instruments.
The ADG1212-EP contains four independent single-pole/
single-throw (SPST) switches. Each switch conducts equally
well in both directions when on and has an input signal range
that extends to the supplies. In the off condition, signal levels up
to the supplies are blocked.
Additional application and technical information can be found
in the ADG1212 data sheet.
PRODUCT HIGHLIGHTS
1. Ultralow capacitance.
2. <1 pC charge injection.
3. 3 V logic compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
4. No VL logic power supply required.
5. Ultralow power dissipation: <0.03 μW.
6. 16-lead TSSOP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
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ADG1212-EP
TABLE OF CONTENTS
Features .............................................................................................. 1 
Enhanced Product Features ............................................................ 1 
Applications....................................................................................... 1 
Functional Block Diagram .............................................................. 1 
General Description ......................................................................... 1 
Product Highlights ........................................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Dual Supply ................................................................................... 3 
REVISION HISTORY
11/11—Revision 0: Initial Version
Enhanced Product
Single Supply..................................................................................4 
Absolute Maximum Ratings ............................................................5 
ESD Caution...................................................................................5 
Pin Configuration and Function Descriptions..............................6 
Typical Performance Characteristics ..............................................7 
Test Circuits........................................................................................9 
Outline Dimensions ....................................................................... 11 
Ordering Guide .......................................................................... 11 
Rev. 0 | Page 2 of 12
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Enhanced Product
ADG1212-EP
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
−40°C to −55°C to
25°C +85°C +125°C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
120
190 230
VDD to VSS
260
On Resistance Match Between Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
2.5
6
20
57
10
72
11
79
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.02
±0.1 ±0.6
±1
Drain Off Leakage, ID (Off )
±0.02
Channel On Leakage, ID, IS (On)
±0.1 ±0.6
±0.02
±0.1 ±0.6
±1
±1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
0.005
2.0
0.8
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
2.5
tON 65
80 95
110
tOFF 80
100 115
135
Charge Injection
−0.3
Off Isolation
80
Channel-to-Channel Crosstalk
90
Total Harmonic Distortion + Noise
0.15
−3 dB Bandwidth
CS (Off )
CD (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
IDD
ISS
ISS
1000
0.9
1.1
1
1.2
2.6
3
0.001
220
0.001
0.001
1.0
420
1.0
1.0
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
Test Conditions/Comments
VS = ±10 V, IS = −1 mA; see Figure 15
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
VS = −5 V/0 V/+5 V; IS = −1 mA
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = m 10 V; see Figure 11
VS = ±10 V, VD = m 10 V; see Figure 11
VS = VD = ±10 V; see Figure 12
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 18
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 18
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 13
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 14
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz;
see Figure 17
RL = 50 Ω, CL = 5 pF; see Figure 16
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
1 Guaranteed by design, not subject to production test.
Rev. 0 | Page 3 of 12
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ADG1212-EP
Enhanced Product
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between Channels (ΔRON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
tOFF
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off )
CD (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
IDD
−40°C to −55°C to
25°C +85°C +125°C Unit
Test Conditions/Comments
300
475 567
4.5
12 26
60
±0.02
±0.1
±0.02
±0.1
±0.02
±0.1
±0.6
±0.6
±0.6
0 V to VDD
625
27
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
nA typ
±1 nA max
nA typ
±1 nA max
nA typ
±1 nA max
VS = 0 V to 10 V, IS = −1 mA; see Figure 15
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
VS = 3 V/6 V/9 V, IS = −1 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 11
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 11
VS = VD = 1 V or 10 V; see Figure 12
0.001
3
2.0
0.8
±0.1
V min
V max
μA typ
μA max
pF typ
VIN = VINL or VINH
80 ns typ RL = 300 Ω, CL = 35 pF
105 125 140 ns max VS = 8 V; see Figure 18
90 ns typ RL = 300 Ω, CL = 35 pF
115 140 165 ns max VS = 8 V; see Figure 18
0 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 19
80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 13
90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 14
900 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 16
1.2 pF typ VS = 6 V, f = 1 MHz
1.4 pF max VS = 6 V, f = 1 MHz
1.3 pF typ VS = 6 V, f = 1 MHz
1.5 pF max VS = 6 V, f = 1 MHz
3.2 pF typ VS = 6 V, f = 1 MHz
3.9 pF max VS = 6 V, f = 1 MHz
VDD = 13.2 V
0.001
μA typ Digital inputs = 0 V or VDD
1.0 μA max
220 μA typ Digital inputs = 5 V
420 μA max
1 Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 12
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