ADC08500 Datasheet PDF - National Semiconductor

www.Datasheet-PDF.com

ADC08500
National Semiconductor

Part Number ADC08500
Description 500 MSPS A/D Converter
Page 30 Pages


ADC08500 datasheet pdf
Download PDF
ADC08500 pdf
View PDF for Mobile

No Preview Available !

June 2007
ADC08500
High Performance, Low Power 8-Bit, 500 MSPS A/D
Converter
General Description
The ADC08500 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 8 bits res-
olution at sampling rates up to 500 MSPS. Consuming a
typical 0.8 Watts at 500 MSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
www.DataSheeftu4lUl o.cpoemrating temperature range. The unique folding and in-
terpolating architecture, the fully differential comparator de-
sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, produc-
ing a high 7.5 ENOB with a 250 MHz input signal and a 500
MHz sample rate while providing a 10-18 B.E.R. Output for-
matting is offset binary and the LVDS digital outputs are
compatible with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
The converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40°C TA +85°C) temperature range.
Features
Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Choice of SDR or DDR output clocking
Multiple ADC Synchronization Capability
Guaranteed No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock
Key Specifications
Resolution
Max Conversion Rate
Bit Error Rate
ENOB @ 250 MHz Input
DNL
Power Consumption
Operating
Power Down Mode
8 Bits
500 MSPS (min)
10-18 (typ)
7.5 Bits (typ)
±0.15 LSB (typ)
0.8 W (typ)
3.5 mW (typ)
Applications
Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
Block Diagram
© 2007 National Semiconductor Corporation 202064
20206453
www.national.com



No Preview Available !

Ordering Information
Industrial Temperature Range
(-40°C < TA < +85°C)
ADC08500CIYB
ADC08500DEV
Pin Configuration
www.DataSheet4U.com
NS Package
128-Pin Exposed Pad LQFP
Development Board
* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.
20206401
www.national.com
2



No Preview Available !

Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
3 OutV / SCLK
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude and
reduced power consumption. See1.1.6 The LVDS Outputs.
When the extended control mode is enabled, this pin functions
as the SCLK input which clocks in the serial data. See 1.2
NORMAL/EXTENDED CONTROL for details on the extended
control mode. See 1.3 THE SERIAL INTERFACE for
description of the serial interface.
www.DataSheet4U.com
OutEdge / DDR /
4 SDATA
15 DCLK_RST
26 PD
30 CAL
14 FSR/ECE
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the
output data transitions. When this pin is floating or connected
to 1/2 the supply voltage, DDR clocking is enabled. See1.1.5.2
Double Data Rate. When the extended control mode is
enabled, this pin functions as the SDATA input. See 1.2
NORMAL/EXTENDED CONTROL for details on the extended
control mode. See 1.3 THE SERIAL INTERFACE for
description of the serial interface.
DCLK Reset. A positive pulse on this pin is used to reset and
synchronize the DCLK outs of multiple converters. See 1.5
MULTIPLE ADC SYNCHRONIZATION for detailed
description.
Power Down Pin. A logic high on the PD pin puts the entire
device into the Power Down Mode.
Calibration Cycle Initiate. A minimum tCAL_L input clock cycles
logic low followed by a minimum of tCAL_H input clock cycles
high on this pin initiates the self calibration sequence. See
2.4.2 Self Calibration for an overview of self-calibration and
2.4.2.2 On-Command Calibration for a description of on-
command calibration.
Full Scale Range Select and Extended Control Enable. In non-
extended control mode, a logic low on this pin sets the full-
scale differential input range to a reduced VIN input level . A
logic high on this pin sets the full-scale differential input range
to a higher VIN input level. See Converter Electrical
Characteristics. To enable the extended control mode,
whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage equal
to VA/2. See 1.2 NORMAL/EXTENDED CONTROL for
information on the extended control mode.
3 www.national.com



No Preview Available !

Pin Functions
Pin No.
Symbol
127 CalDly / SCS
Equivalent Circuit
Description
Calibration Delay and Serial Interface Chip Select. With a logic
high or low on pin 14, this pin functions as Calibration Delay
and sets the number of clock cycles after power up before
calibration begins. See 1.1.1 Self-Calibration. With pin 14
floating, this pin acts as the enable pin for the serial interface
input and the CalDly value becomes "0" (short delay with no
provision for a long power-up calibration delay).
www.DataSheet4U.com
18
19
CLK+
CLK-
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See1.1.2 Acquiring the
Input for a description of acquiring the input and 2.3 THE
CLOCK INPUTS for an overview of the clock inputs.
11 VIN+
10 VIN
7 VCMO
31 VBG
126 CalRun
Analog signal inputs to the ADC. The differential full-scale
input range of this input is programmable using the FSR pin
14 in normal mode and the Input Full-Scale Voltage Adjust
register in the extended control mode. Refer to the VIN
specification in the Converter Electrical Characteristics for the
full-scale input range in the normal mode. Refer to 1.4
REGISTER DESCRIPTION for the full-scale input range in the
extended control mode.
Common Mode Voltage. This pin is the common mode output
in d.c. coupling mode and also serves as the a.c. coupling
mode select pin. When d.c. coupling is used, the voltage
output at this pin is required to be the common mode input
voltage at VIN+ and VIN− when d.c. coupling is used. This pin
should be grounded when a.c. coupling is used at the analog
inputs. This pin is capable of sourcing or sinking 100 μA. See
2.2 THE ANALOG INPUT.
Bandgap output voltage capable of 100 μA source/sink.
Calibration Running indication. This pin is at a logic high when
calibration is running.
www.national.com
4



ADC08500 datasheet pdf
Download PDF
ADC08500 pdf
View PDF for Mobile


Related : Start with ADC0850 Part Numbers by
ADC08500 500 MSPS A/D Converter ADC08500
National Semiconductor
ADC08500 pdf
ADC08500 ADC08500 High Performance Low Power 8-Bit 500 MSPS A/D Converter (Rev. E) ADC08500
Texas Instruments
ADC08500 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact