AD9277 Datasheet PDF - Analog Devices

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AD9277
Analog Devices

Part Number AD9277
Description Octal LNA/VGA/AAF/14-Bit ADC And CW I/Q Demodulator
Page 30 Pages


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Octal LNA/VGA/AAF/14-Bit ADC
and CW I/Q Demodulator
AD9277
FEATURES
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
Low noise preamplifier (LNA)
Input-referred noise: 0.75 nV/√Hz typical at 5 MHz
(gain = 21.3 dB)
SPI-programmable gain: 15.6 dB/17.9 dB/21.3 dB
Single-ended input: VIN maximum = 733 mV p-p/
550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output: 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range: −42 dB to 0 dB
Postamp gain: 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable second-order LPF from 8 MHz to 18 MHz
Programmable HPF
Analog-to-digital converter (ADC)
14 bits at 10 MSPS to 50 MSPS
SNR: 73 dB
SFDR: 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
CW mode I/Q demodulator
Individual programmable phase rotation
Output dynamic range per channel >160 dBFS/√Hz
Low power: 207 mW per channel at 14 bits/50 MSPS (TGC),
94 mW per channel for CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode: <2 μs
100-lead TQFP_EP
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
PRODUCT HIGHLIGHTS
1. Small Footprint.
Eight channels are contained in a small, space-saving
package. Full TGC path, ADC, and I/Q demodulator
contained within a 100-lead, 16 mm × 16 mm TQFP.
2. Low Power.
In TGC mode, low power of 207 mW per channel
at 50 MSPS. In CW mode, ultralow power of 94 mW
per channel.
3. Integrated High Dynamic Range I/Q Demodulator with
Phase Rotation.
4. Ease of Use.
A data clock output (DCO±) operates up to 480 MHz
and supports double data rate (DDR) operation.
5. User Flexibility.
Serial port interface (SPI) control offers a wide range of
flexible features to meet specific system requirements.
6. Integrated Second-Order Antialiasing Filter.
This filter is placed before the ADC and is programmable
from 8 MHz to 18 MHz.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 PDWN STBY
DRVDD
LO-A TO LO-H
LOSW-A TO LOSW-H
LI-A TO LI-H
LG-A TO LG-H
LNA
I/Q
DEMODULATOR
VGA
AAF
8 CHANNELS
14-BIT
ADC
SERIAL
LVDS
DOUTA+ TO DOUTH+
DOUTA– TO DOUTH–
LO
GENERATION
REFERENCE
SERIAL
PORT
INTERFACE
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.



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TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Product Highlights ........................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
General Description ......................................................................... 3 
Specifications..................................................................................... 4 
AC Specifications.......................................................................... 4 
Digital Specifications ................................................................... 7 
Switching Specifications .............................................................. 8 
ADC Timing Diagrams ............................................................... 9 
Absolute Maximum Ratings.......................................................... 10 
Thermal Impedance ................................................................... 10 
ESD Caution................................................................................ 10 
Pin Configuration and Function Descriptions........................... 11 
Typical Performance Characteristics ........................................... 14 
TGC Mode................................................................................... 14 
CW Doppler Mode..................................................................... 17 
Equivalent Circuits ......................................................................... 19 
Theory of Operation ...................................................................... 21 
REVISION HISTORY
7/09—Revision 0: Initial Version
Ultrasound .................................................................................. 21 
Channel Overview ..................................................................... 22 
Input Overdrive .......................................................................... 25 
CW Doppler Operation............................................................. 25 
TGC Operation........................................................................... 29 
ADC ............................................................................................. 33 
Clock Input Considerations...................................................... 33 
Digital Outputs and Timing ..................................................... 35 
Serial Port Interface (SPI).............................................................. 39 
Hardware Interface..................................................................... 40 
Memory Map .................................................................................. 41 
Reading the Memory Map Table.............................................. 41 
Reserved Locations .................................................................... 41 
Default Values ............................................................................. 41 
Logic Levels................................................................................. 41 
Applications Information .............................................................. 45 
Power and Ground Recommendations ................................... 45 
Exposed Paddle Thermal Heat Slug Recommendations ...... 45 
Outline Dimensions ....................................................................... 46 
Ordering Guide .......................................................................... 46 
Rev. 0 | Page 2 of 48



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GENERAL DESCRIPTION
The AD9277 is designed for low cost, low power, small size,
and ease of use. It contains eight channels of a variable gain
amplifier (VGA) with a low noise preamplifier (LNA); an anti-
aliasing filter (AAF); a 14-bit, 10 MSPS to 50 MSPS analog-to-
digital converter (ADC); and an I/Q demodulator with
programmable phase rotation.
Each channel features a variable gain range of 42 dB, a fully differ-
ential signal path, an active input preamplifier termination, a
maximum gain of up to 52 dB, and an ADC with a conversion
rate of up to 50 MSPS. The channel is optimized for dynamic
performance and low power in applications where a small
package size is critical.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. The LNA input noise is typically 0.75 nV/√Hz
at a gain of 21.3 dB, and the combined input-referred noise of
the entire channel is 0.85 nV/√Hz at maximum gain. Assuming
a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the
input SNR is roughly 92 dB. In CW Doppler mode, each LNA
output drives an I/Q demodulator. Each demodulator has inde-
pendently programmable phase rotation through the SPI with
16 phase settings.
The AD9277 requires a LVPECL-/CMOS-/LVDS-compatible
sample rate clock for full performance operation. No external
reference or driver components are required for many applications.
AD9277
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO±) for
capturing data on the output and a frame clock (FCO±) trigger
for signaling a new output byte are provided.
Powering down individual channels is supported to increase
battery life for portable applications. A standby mode option
allows quick power-up for power cycling. In CW Doppler opera-
tion, the VGA, AAF, and ADC are powered down. The power of
the TGC path scales with selectable ADC speed power modes.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as a programmable clock, data
alignment, and programmable digital test pattern generation. The
digital test patterns include built-in fixed patterns, built-in pseudo-
random patterns, and custom user-defined test patterns entered
via the serial port interface.
Fabricated in an advanced CMOS process, the AD9277 is
available in a 16 mm × 16 mm, RoHS compliant, 100-lead
TQFP. It is specified over the industrial temperature range
of −40°C to +85°C.
Rev. 0 | Page 3 of 48



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SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high,
PGA gain = 24 dB, GAIN− = 0.8 V, AAF LPF cutoff = fSAMPLE/4.5, HPF cutoff = LPF cutoff/20.7 (default), fSAMPLE = 50 MSPS (Register 0x02 = 0x01),
full temperature, ANSI-644 LVDS mode, unless otherwise noted.
Table 1.
Parameter1
LNA CHARACTERISTICS
Gain
Input Voltage Range
(Single-Ended)
Input Common Mode (LI-x, LG-x)
Output Common Mode (LO-x)
Output Common Mode (LOSW-x)
Input Resistance (LI-x)
Input Capacitance (LI-x)
−3 dB Bandwidth
Input Noise Voltage
Input Noise Current
1 dB Input Compression Point
Noise Figure
Active Termination Matched
Unterminated
FULL-CHANNEL (TGC)
CHARACTERISTICS
AAF Low-Pass Cutoff
In Range
In Range AAF Bandwidth
Tolerance
Group Delay Variation
Input-Referred Noise Voltage
Test Conditions/Comments
Single-ended input to differential output
Single-ended input to single-ended output
LNA output limited to 4.4 V p-p differential
output
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
Switch off
Switch on
RFB = 250 Ω
RFB = 500 Ω
RFB = ∞
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RFB = ∞
GAIN+ = 0 V
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RS = 50 Ω
LNA gain = 15.6 dB, RFB = 200 Ω
LNA gain = 17.9 dB, RFB = 250 Ω
LNA gain = 21.3 dB, RFB = 350 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.3 dB, RFB = ∞
−3 dB, programmable
f = 1 MHz to 18 MHz, GAIN+ = 0 V to 1.6 V
GAIN+ = 1.6 V, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
Min
8
Typ Max
15.6/17.9/21.3
9.6/11.9/15.3
733
550
367
1.0
1.5
High-Z
1.5
50
100
15
22
100
0.98
0.86
0.75
1
1.0
0.8
0.5
4.8
4.1
3.2
3.4
2.8
2.3
18
±10
±2
1.26
1.04
0.85
Unit
dB
dB
mV p-p
mV p-p
mV p-p
V
V
Ω
V
Ω
Ω
pF
MHz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
V p-p
V p-p
V p-p
dB
dB
dB
dB
dB
dB
MHz
%
ns
nV/√Hz
nV/√Hz
nV/√Hz
Rev. 0 | Page 4 of 48



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