AD9272 Datasheet PDF - Analog Devices

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AD9272
Analog Devices

Part Number AD9272
Description Octal LNA/VGA/AAF/ADC and Crosspoint Switch
Page 30 Pages


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FEATURES
8 channels of LNA, VGA, AAF, and ADC
Low noise preamplifier (LNA)
Input-referred noise voltage = 0.75 nV/√Hz
(gain = 21.3 dB) @ 5 MHz typical
SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB
Single-ended input; VIN maximum = 733 mV p-p/
550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output = 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range = −42 dB to 0 dB
SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable 2nd-order low-pass filter (LPF) from
8 MHz to 18 MHz
Programmable high-pass filter (HPF)
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 80 MSPS
SNR = 70 dB
SFDR = 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
Includes an 8 × 8 differential crosspoint switch to support
continuous wave (CW) Doppler
Low power, 195 mW per channel at 12 bits/40 MSPS (TGC)
120 mW per channel in CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode, <2 μs
100-lead TQFP
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
GENERAL DESCRIPTION
The AD9272 is designed for low cost, low power, small size, and
ease of use. It contains eight channels of a low noise preamplifier
(LNA) with a variable gain amplifier (VGA), an antialiasing
filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-to-
digital converter (ADC).
Each channel features a variable gain range of 42 dB, a fully
differential signal path, an active input preamplifier termination, a
maximum gain of up to 52 dB, and an ADC with a conversion
rate of up to 80 MSPS. The channel is optimized for dynamic
performance and low power in applications where a small
package size is critical.
Octal LNA/VGA/AAF/ADC
and Crosspoint Switch
AD9272
FUNCTIONAL BLOCK DIAGRAM
LOSW-A
LO-A
LI-A
LG-A
LNA
VGA
LOSW-B
LO-B
LI-B
LG-B LNA VGA
LOSW-C
LO-C
LI-C
LG-C LNA VGA
LOSW-D
LO-D
LI-D
LG-D
LNA
VGA
LOSW-E
LO-E
LI-E
LG-E
LNA
VGA
LOSW-F
LO-F
LI-F
LG-F LNA VGA
LOSW-G
LO-G
LI-G
LG-G
LNA
VGA
LOSW-H
LO-H
LI-H
LG-H LNA VGA
SWITCH
ARRAY
AD9272
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTA+
DOUTA–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTB+
DOUTB–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTC+
DOUTC–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTD+
DOUTD–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTE+
DOUTE–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTF+
DOUTF–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTG+
DOUTG–
AAF
12-BIT
ADC
REFERENCE
SERIAL
LVDS
DOUTH+
DOUTH–
FCO+
FCO–
DCO+
DCO–
Figure 1.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. The LNA input-referred noise voltage is typically
0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred
noise voltage of the entire channel is 0.85 nV/√Hz at maximum
gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB
LNA gain, the input SNR is about 92 dB. In CW Doppler mode,
the LNA output drives a transconductance amp that is switched
through an 8 × 8 differential crosspoint switch. The switch is
programmable through the SPI.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.



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AD9272* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
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Evaluation Kits
• AD9272 Evaluation Board
Documentation
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-1210: Powering the AD9272 Octal Ultrasound ADC/
LNA/VGA/AAF with the ADP5020 Switching Regulator
PMU for Increased Efficiency
• AN-586: LVDS Outputs for High Speed A/D Converters
• AN-737: How ADIsimADC Models an ADC
• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD9272: Octal LNA/VGA/AAF/ADC and Crosspoint
Switch Data Sheet
Software and Systems Requirements
• UG-001: Evaluation Board User Guide
Tools and Simulations
• Visual Analog
• AD9272 IBIS Models
Reference Materials
Press
• Industry’s First Octal Ultrasound Receiver with Digital I/Q
Demodulator and Decimation Filter Reduces Processor
Overhead in Ultrasound Systems
• Low Cost, Octal Ultrasound Receiver with On-Chip RF
Decimator and JESD204B Serial Interface
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
• New Components Offer Fexibility in Ultrasound System
Design
• Powering High-Speed Analog-to-Digital Converters with
Switching Power Supplies
• Processors for Ultrasound Improve Image Quality
Design Resources
• AD9272 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
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Technical Support
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AD9272
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications..................................................................................... 4
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 8
Switching Specifications .............................................................. 9
Absolute Maximum Ratings.......................................................... 11
Thermal Impedance ................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 15
Equivalent Circuits ......................................................................... 19
Theory of Operation ...................................................................... 21
REVISION HISTORY
7/09—Rev. B to Rev. C
Changes to Input Overload Protection Section and Figure 43 .......25
Changes to Digital Outputs and Timing Section and Changes
to Figure 63...................................................................................... 33
Changes to Hardware Interface Section ...................................... 39
6/09—Rev. A to Rev. B
Changes to Product Highlights Section......................................... 3
Changes to Table 1............................................................................ 4
Changes to Absolute Maximum Ratings Table........................... 11
Changes to Figure 22...................................................................... 17
Changes to Figure 33 and Figure 34............................................. 20
Changes to Low Noise Amplifier (LNA) Section....................... 22
Changes to Active Impedance Matching Section....................... 23
Changes to Figure 39...................................................................... 23
Changes to LNA Noise Section..................................................... 24
Changes to Figure 47...................................................................... 28
Changes to Figure 48 and Figure 49............................................. 29
Changes to CSB Pin Section.......................................................... 36
Changes to Reading the Memory Map Table Section................ 40
4/09—Revision A: Initial Version
Ultrasound .................................................................................. 21
Channel Overview ..................................................................... 22
Input Overdrive .......................................................................... 25
CW Doppler Operation............................................................. 25
TGC Operation........................................................................... 27
ADC ............................................................................................. 31
Clock Input Considerations...................................................... 31
Serial Port Interface (SPI).............................................................. 38
Hardware Interface..................................................................... 38
Memory Map .................................................................................. 40
Reading the Memory Map Table.............................................. 40
Reserved Locations .................................................................... 40
Default Values ............................................................................. 40
Logic Levels................................................................................. 40
Outline Dimensions ....................................................................... 44
Ordering Guide .......................................................................... 44
Rev. C | Page 2 of 44



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The AD9272 requires a LVPECL-/CMOS-/LVDS-compatible
sample rate clock for full performance operation. No external
reference or driver components are required for many
applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO±) for
capturing data on the output and a frame clock (FCO±) trigger
for signaling a new output byte are provided.
Powering down individual channels is supported to increase
battery life for portable applications. There is also a standby
mode option that allows quick power-up for power cycling. In
CW Doppler operation, the VGA, antialiasing filter (AAF), and
ADC are powered down. The power of the time gain control
(TGC) path scales with selectable speed grades.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as a programmable clock, data
alignment, and programmable digital test pattern generation. The
digital test patterns include built-in fixed patterns, built-in
pseudorandom patterns, and custom user-defined test patterns
entered via the serial port interface.
AD9272
Fabricated in an advanced CMOS process, the AD9272 is
available in a 16 mm × 16 mm, RoHS-compliant, 100-lead
TQFP. It is specified over the industrial temperature range of
−40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight channels are contained in a
small, space-saving package. A full TGC path, ADC, and
crosspoint switch are contained within a 100-lead, 16 mm ×
16 mm TQFP.
2. Low Power of 195 mW Per Channel at 40 MSPS.
3. Integrated Crosspoint Switch. This switch allows numerous
multichannel configuration options to enable the CW
Doppler mode.
4. Ease of Use. A data clock output (DCO±) operates up to
480 MHz and supports double data rate (DDR) operation.
5. User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
6. Integrated Second-Order Antialiasing Filter. This filter is
placed between the VGA and the ADC and is programmable
from 8 MHz to 18 MHz.
Rev. C | Page 3 of 44



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