A3988 Datasheet PDF - Allegro MicroSystems

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A3988
Allegro MicroSystems

Part Number A3988
Description Quad DMOS Full Bridge PWM Motor Driver
Page 13 Pages


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A3988
Quad DMOS Full Bridge PWM Motor Driver
Features and Benefits
36 V output rating
4 full bridges
Dual stepper motor driver
High current outputs
3.3 and 5 V compatible logic supply
Synchronous rectification
Internal undervoltage lockout (UVLO)
Thermal shutdown circuitry
Crossover-current protection
Low profile QFN package
Packages
Package EV, 36 pin QFN
0.90 mm nominal height
with exposed thermal pad
Package JP, 48 pin LQFP
with exposed thermal pad
Approximate scale
Description
The A3988 is a quad DMOS full-bridge driver capable of
driving up to two stepper motors or four dc motors. Each
full-bridge output is rated up to 1.2 A and 36 V. The A3988
includes fixed off-time pulse width modulation (PWM) current
regulators, along with 2- bit nonlinear DACs (digital-to-analog
converters) that allow stepper motors to be controlled in full,
half, and quarter steps, and dc motors in forward, reverse, and
coast modes. The PWM current regulator uses the Allegro®
patented mixed decay mode for reduced audible motor noise,
increased step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Protection features include thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover current protection.
Special power up sequencing is not required.
The A3988 is supplied in two packages, EV and JP, with
exposed power tabs for enhanced thermal performance. The
EV is a 6 mm x 6 mm, 36 pin QFN package with a nominal
overall package height of 0.90 mm. The JP is a 7 mm × 7 mm
48 pin LQFP. Both packages are lead (Pb) free, with 100%
matte tin leadframe plating.
A3988DS, Rev.3
Microprocessor
VREF
VDD 3.3 V
0.1 μF
50 V
0.1 μF
50 V
100 μF
50 V
VMOTOR 32 V
0.22 μF
50 V
PHASE1
I01
I11
PHASE2
I02
I12
PHASE3
I03
I13
PHASE4
I04
I14
VREF1
VREF2
VREF3
VREF4
VDD
A3988
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
SENSE2
SENSE1
SENSE3
SENSE4
Bipolar Stepper Motors
RS2
RS1
RS3
RS4
Figure 1. Typical application circuit



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A3988
Quad DMOS Full Bridge PWM Motor Driver
Selection Guide
Part Number
A3988SEV-T
Package
36 pin QFN with exposed thermal pad
A3988SEVTR-T
36 pin QFN with exposed thermal pad
A3988SJP-T
48 pin LQFP with exposed thermal pad
Packing
61 pieces per tube
1500 pieces per reel
250 pieces per tray
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Symbol
VBB
Logic Supply Voltage
Output Current
VDD
IOUT
Logic Input Voltage Range
SENSEx Pin Voltage
VIN
VSENSEx
VREFx Pin Voltage
Operating Temperature Range
Junction Temperature
Storage Temperature Range
VREFx
TA
TJ(max)
Tstg
Notes
Pulsed tw < 1 μs
May be limited by duty cycle, ambient temperature, and heat sinking. Under
any set of conditions, do not exceed the specified current rating or a Junction
Temperature of 150°C.
Pulsed tw < 1 μs
Pulsed tw < 1 μs
Range S
Rating
-0.5 to 36
38
–0.4 to 7
1.2
Units
V
V
V
A
2.8
–0.3 to 7
0.5
2.5
2.5
–20 to 85
150
–40 to 125
A
V
V
V
V
ºC
ºC
ºC
Thermal Characteristics (may require derating at maximum conditions)
Characteristic
Symbol
Test Conditions
Package Thermal Resistance
EV package, 4 layer PCB based on JEDEC standard
RθJA JP package, 4 layer PCB based on JEDEC standard
Power Dissipation versus Ambient Temperature
5500
5000
4500
4000
3500
JP Package
4-layer PCB
(RQJA = 23 ºC/W)
3000
2500
2000
1500
EV Package
4-layer PCB
(RQJA = 27 ºC/W)
1000
500
0
25 50 75 100 125 150 175
Temperature (°C)
Min. Units
27 ºC/W
23 ºC/W
Allegro MicroSystems, Inc.
2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com



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A3988
Quad DMOS Full Bridge PWM Motor Driver
Functional Block Diagram
0.1 μF
50 V
VDD
OSC
PHASE1
I01
I11
PHASE2
I02
I12
VREF1
Sense1
3
VREF2
3
Sense2
PHASE3
I03
I13
PHASE4
I04
I14
VREF3
Sense3
3
VREF4
3
Sense4
CHARGE PUMP
Control Logic
Bridges 1 and 2
PWM Latch
BLANKING
PWM Latch
BLANKING
Control Logic
Bridges 3 and 4
PWM Latch
BLANKING
PWM Latch
BLANKING
0.1 μF
50 V
DMOS
VBB1
FULL-BRIDGE 1
VCP
100 μF
50 V
OUT1A
OUT1B
0.22 μF
50 V
To
VBB2
GATE
DRIVE
DMOS
VBB1
FULL-BRIDGE 2
SENSE1
OUT2A
OUT2B
VCP
GATE
DRIVE
Sense2
SENSE2
DMOS
FULL-BRIDGE 3
VBB2
OUT3A
OUT3B
Sense3
SENSE3
VBB2
DMOS
FULL-BRIDGE 4
Sense4
OUT4A
OUT4B
SENSE4
Allegro MicroSystems, Inc.
3
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com



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A3988
Quad DMOS Full Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS1, valid at TA = 25°C, VBB = 36 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Load Supply Voltage Range
Logic Supply Voltage Range
VDD Supply Current
Output On Resistance
Vf , Outputs
Output Leakage
VBB Supply Current
VBB
VDD
IDD
RDS(on)
IDSS
IBB
Operating
Operating
Source driver, IOUT = –1.2 A, TJ = 25°C
Sink driver, IOUT = 1.2 A, TJ = 25°C
IOUT = 1.2 A
Outputs, VOUT = 0 to VBB
IOUT = 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
Min.
8.0
3.0
–20
Typ.2
7
700
700
Max.
36
5.5
10
800
800
1.2
20
8
Units
V
V
mA
mΩ
mΩ
V
μA
mA
Control Logic
Logic Input Voltage
Logic Input Current
Input Hysteresis
Propagation Delay Times
Crossover Delay
Blank Time
VREFx Pin Input Voltage Range
VREFx Pin Reference Input Current
Current Trip-Level Error3
Protection Circuits
VBB UVLO Threshold
VBB Hysteresis
VDD UVLO Threshold
VDD Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VIN(1)
VIN(0)
IIN
Vhys
tpd
tCOD
tBLANK
VREFx
IREF
VERR
VIN = 0 to 5 V
PWM change to source on
PWM change to source off
PWM change to sink on
PWM change to sink off
Operating
VREF = 1.5
VREF = 1.5, phase current = 100%
VREF = 1.5, phase current = 67%
VREF = 1.5, phase current = 33%
VUV(VBB)
VUV(VBB)hys
VUV(VDD)
VUV(VDD)hys
TJTSD
TJTSDhys
VBB rising
VDD rising
0.7×VDD
–20
150
350
35
350
35
300
0.7
0.0
–5
–5
–15
<1.0
300
550
550
425
1
0.3×VDD
20
500
1000
300
1000
250
1000
1.3
1.5
±1
5
5
15
7.3 7.6 7.9
400 500 600
2.65 2.8 2.95
75 105 125
155 165 175
– 15 –
V
V
μA
mV
ns
ns
ns
ns
ns
μs
V
μA
%
%
%
V
mV
V
mV
°C
°C
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
3VERR = [(VREF/3) – VSENSE] / (VREF/3).
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com



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