84330CI Datasheet PDF - IDT

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84330CI
IDT

Part Number 84330CI
Description Crystal-to-LVPECL Frequency Synthesizer
Page 20 Pages


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720MHz, Low Jitter, Crystal-to-LVPECL
Frequency Synthesizer
84330CI
Data Sheet
General Description
The 84330CI is a general purpose, single output high frequency
synthesizer. The VCO operates at a frequency range of 250MHz to
720MHz. The VCO and output frequency can be programmed using
the serial or parallel interfaces to the configuration logic. The output
can be configured to divide the VCO frequency by 1, 2, 4, and 8.
Output frequency steps as small as 250kHz to 2MHz can be
achieved using a 16MHz crystal depending on the output divider
settings.
Features
Fully integrated PLL, no external loop filter requirements
One differential 3.3V LVPECL output
Crystal oscillator interface: 10MHz to 25MHz
Output frequency range: 31.25MHz to 720MHz
VCO range: 250MHz to 720MHz
Parallel or serial interface for programming M and N dividers
during power-up
RMS period jitter: 6ps (maximum)
Cycle-to-cycle jitter: 40ps (maximum)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Pin Assignments
Block Diagram
OE
XTAL1
XTAL2
FREF_EXT
Pullup
OSC
Pulldown
XTAL_SEL
Pullup
1
0
÷ 16
PLL
PHASE DETECTOR
VCO
÷M ÷2
÷2
1
÷4
÷8
÷1
0
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
Pulldown
Pulldown
Pulldown
Pullup
M0:M8
N0:N1
Pullup
Pullup
CONFIGURATION
INTERFACE
LOGIC
FOUT
nFOUT
TEST
25 24 23 22 21 20 19
S_CLOCK
S_DATA
S_LOAD
VCCA
FREF_EXT
XTAL_SEL
XTAL1
26 18
27 ICS84330CI 17
28 28 Lead PLCC 16
1
V Package
15
11.6mm x 11.4mm x 4.1mm
2
package body
14
3
Top View
13
4 12
5 6 7 8 9 10 11
N1
N0
M8
M7
M6
M5
M4
32 31 30 29 28 27 26 25
S_CLOCK 1
24 nc
S_DATA 2
S_LOAD 3
VCCA 4
VCCA 5
FREF_EXT 6
XTAL_SEL 7
ICS84330CI
32 Lead LQFP
Y Package
7mm x 7mm x 1.4mm
package body
Top View
23 N1
22 N0
21 M8
20 M7
19 M6
18 M5
XTAL1 8
17 M4
9 10 11 12 13 14 15 16
©2016 Integrated Device Technology, Inc
1
Revision A January 13, 2016



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84330CI Data Sheet
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 6, NOTE 1.
The 84330CI features a fully integrated PLL and therefore requires
no external components for setting the loop bandwidth. A quartz
crystal is used as the input to the on-chip oscillator. The output of the
oscillator is divided by 16 prior to the phase detector. With a 16MHz
crystal, this provides a 1MHz reference frequency. The VCO of the
PLL operates over a range of 250MHz to 720MHz. The output of the
M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the 84330CI support two input modes
to program the M divider and N output divider. The two input
operational modes are parallel and serial. Figure 1 shows the timing
diagram for each mode. In parallel mode the nP_LOAD input is
LOW. The data on inputs M0 through M8 and N0 through N1 is
passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. The TEST output is Mode
000 (shift register out) when operating in the parallel input mode.
The relationship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
fVCO = fXTAL x 2M
16
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock are defined as 125 M 
360. The frequency out is defined as follows:
fout = fVCO = fXTAL x 2M
N 16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider when S_LOAD transitions from
LOW-to-HIGH. The M divide and N output divide values are latched
on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held
HIGH, data at the S_DATA input is passed directly to the M divider
on each rising edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T2:T0. The internal registers
T2:T0 determine the state of the TEST output as follows in the table
below:
T2 T1 T0 TEST Output
fOUT
0 0 0 Shift Register Out
fOUT
0 0 1 HIGH
fOUT
0 1 0 PLL Reference XTAL ÷16
fOUT
0 1 1 (VCO ÷ M)/2 (non 50% Duty Cycle M Divider)
fOUT
1 0 0 fOUT, LVCMOS Output Frequency < 200MHz
fOUT
1 0 1 LOW
fOUT
1 1 0 (S_CLOCK ÷ M)/2 (non 50% Duty Cycle M Divider) S_CLOCK ÷ N Divider
1 1 1 fOUT ÷ 4
fOUT
S_CLOCK
SERIAL LOADING
S_DATA
S_LOAD
T2 T1
tt
SH
T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
nP_LOAD
M0:M8, N0:N1
nP_LOAD
nP_LOAD
Figure 1. Parallel & Serial Load Operations
©2016 Integrated Device Technology, Inc
M, N
PARALLEL LOADING
tt
SH
Time
2
t
S
Revision A January 13, 2016



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84330CI Data Sheet
Table 1. Pin Descriptions
Name
VCCA
XTAL1, XTAL2
XTAL_SEL
OE
nP_LOAD
Type
Power
Input
Input
Input
Pullup
Pullup
Pullup
Description
Analog supply pin.
Crystal oscillator interface. XTAL1 is an oscillator input, XTAL2 is an oscillator output.
Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW.
LVCMOS / LVTTL interface levels.
Output enable. LVCMOS / LVTTL interface levels.
Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and
when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
M0, M1, M2
M3, M4, M5
M6, M7, M8
N0, N1
VEE
TEST
VCC
nFOUT, FOUT
nc
FREF_EXT
S_CLOCK
S_DATA
S_LOAD
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS /
LVTTL interface levels.
Input
Power
Output
Power
Output
Unused
Input
Input
Input
Input
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
Single-ended LVPECL interface levels.
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
No connect.
PLL reference input. LVCMOS / LVTTL interface levels.
Clocks the serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc
3
Revision A January 13, 2016



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84330CI Data Sheet
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
nP_LOAD M
N S_LOAD S_CLOCK S_DATA
X XX X X X
L
Data Data
X
X
X
Data Data L X X
H XX L
Data
H XX
H XX
H XX L
H
XX
H
NOTE:
L = LOW
H = HIGH
X = Don’t care
= Rising edge transition
= Falling edge transition
L Data
L Data
XX
Data
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to the M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded until next
LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on S_DATA on
each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider and
N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
Table 3B. Programmable VCO Frequency Function Table
VCO Frequency
256 128
64
32
16
8
4
2
1
(MHz)
M Divide
M8
M7
M6
M5
M4
M3
M2
M1
M0
250 125 0 0 1 1 1 1 1 0 1
252 126 0 0 1 1 1 1 1 1 0
254 127 0 0 1 1 1 1 1 0 1
256 128 0 1 0 0 0 0 0 1 0
• • •••••••••
• • •••••••••
718 359 1 0 1 1 0 0 1 1 1
720 360 1 0 1 1 0 1 0 0 0
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
Table 3C. Programmable Output DividerFunction Table
Inputs
N1 N0 N Divider Value
00
2
01
4
10
8
11
1
Output Frequency (MHz)
Minimum
Maximum
125 360
62.5 180
31.25
90
250 720
©2016 Integrated Device Technology, Inc
4
Revision A January 13, 2016



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84330CI Crystal-to-LVPECL Frequency Synthesizer 84330CI
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