813N252DI-02 Datasheet PDF - IDT

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813N252DI-02
IDT

Part Number 813N252DI-02
Description Jitter Attenuator & FemtoClock NG Multiplier
Page 23 Pages


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Jitter Attenuator & FemtoClock NG®
Multiplier
813N252DI-02
DATA SHEET
General Description
Features
The 813N252DI-02 device uses IDT's fourth generation
FemtoClock® NG technology for optimal high clock frequency and
low phase noise performance, combined with a low power
consumption and high power supply noise rejection. The
813N252DI-02 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation.
The813N252DI-02 is a fully integrated Phase Locked loop utilizing a
FemtoClock NG Digital VCXO that provides the low jitter, high
frequency SONET/PDH output clock that easily meets OC-48 jitter
requirements. This VCXO technology simplifies PLL design by
replacing the pullable crystal requirement of analog VCXOs with a
fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is
provided by an external loop filter. Pre-divider and output divider
multiplication ratios are selected using device selection control pins.
The multiplication ratios are optimized to support most common
clock rates used in PDH, SONET and Ethernet applications. The
device requires the use of an external, inexpensive fundamental
mode 27MHz crystal. The device is packaged in a space-saving
32-VFQFN package and supports industrial temperature range.
Pin Assignment
LF1
32 31 30 29 28 27 26 25
1 24
Fourth generation FemtoClock® NG technology
Two LVPECL output pairs
Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
Crystal interface optimized for a 27MHz, 10pF parallel resonant
crystal
Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode crystal
Customized settings for jitter attenuation and reference tracking
using an external loop filter connection
FemtoClock NG frequency multiplier provides low jitter, high
frequency output
Absolute pull range: ±100ppm
Power supply noise rejection (PSNR): -85dB (typical)
FemtoClock NG VCXO frequency: 2500MHz
RMS phase jitter @ 156.25MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.6ps (typical)
RMS phase jitter @ 125MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.65ps (typical)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
VEE
LF0 2
23 nQB
ISET 3
22 QB
VEE
CLK_SEL
4
5
813N252DI-02
21 VCCO
20 nQA
VCC
RESERVED
VEE
6
7
8
9
19
18
17
10 11 12 13 14 15 16
QA
VEE
ODASEL_0
32-pin, 5mm x 5mm VFQFN Package
REVISION 1 08/14/15
1
©2015 INTEGRATED DEVICE TECHNOLOGY, INC.



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Block Diagram
PDSEL_[2:0]
CLK_SEL
Pullup
Pulldown
CLK0
nCLK0
Pulldown
Pullup /
Pulldown
CLK1
nCLK1
Pulldown
Pullup /
Pulldown
3
0
÷P
1
Phase
Detector
+
Charge
Pump
÷M
813N252DI-02 DATA SHEET
27MHz
Xtal
Osc.
PD
+
LF
DIGITAL
VCXO
FemtoClock NG
VCO
Fractional
Feedback
Divider
A / D Control
Block
2
Pulldown
÷NA
ODASEL_[1:0]
QA
nQA
÷NB
2
Pulldown
QB
nQB
ODBSEL_[1:0]
*** Dashed lines indicates external components
REVISION 1 08/14/15
2 JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER



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813N252DI-02 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
LF1, LF0
Analog
Input/Output
Loop filter connection node pins. LF0 is the output. LF1 is the input.
3
ISET
Analog
Input/Output
Charge pump current setting pin.
4, 8, 18, 24
5
VEE
CLK_SEL
Power
Input
Pulldown
Negative supply pins.
Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS / LVTTL interface levels.
6, 12, 27
7
VCC
RESERVED
Power
Reserve
Core supply pins.
Reserved pin.
9, PDSEL_2,
10,
PDSEL_1,
Input
11 PDSEL_0
Pullup
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
13
VCCA
Power
Analog supply pin.
14,
15
ODBSEL_1,
ODBSEL_0
Input
Pulldown
Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
16,
17
ODASEL_1,
ODASEL_0
Input
Pulldown
Frequency select pins for Bank A output. See Table 3B.
LVCMOS/LVTTL interface levels.
19, 20
QA, nQA
Output
Differential Bank A clock outputs. LVPECL interface levels.
21
22, 23
VCCO
QB, nQB
Power
Output
Output supply pin.
Differential Bank B clock outputs. LVPECL interface levels.
25
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
26
CLK1
Input
Pulldown Non-inverting differential clock input.
28
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
29
CLK0
Input
Pulldown Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
32
VCCX
Power
Power supply pin for the crystal oscillator.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
3
REVISION 1 08/14/15



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Function Tables
Table 3A. Pre-Divider Selection Function Table
PDSEL_2
0
0
0
0
1
1
1
1
Inputs
PDSEL_1
0
0
1
1
0
0
1
1
PDSEL_0
0
1
0
1
0
1
0
1
÷P Value
1
193
256
1944
2500
7776
12500
15552 (default)
Table 3B. Output Divider Function Table
Inputs
ODxSEL_1 ODxSEL_0
÷Nx Value
00
100 (default)
01
20
10
16
11
8
NOTE: x denotes A or B.
813N252DI-02 DATA SHEET
REVISION 1 08/14/15
4 JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER



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