80960KA Datasheet PDF - Intel Corporation


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80960KA
Intel Corporation

Part Number 80960KA
Description EMBEDDED 32-BIT MICROPROCESSOR
Page 30 Pages

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80960KA
EMBEDDED 32-BIT MICROPROCESSOR
s High-Performance Embedded Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at 25 MHz
s 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached Instruc-
tions
s Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored On-Chip
— Register Scoreboarding
s 4 Gigabyte, Linear Address Space
s Pin Compatible with 80960KB
s Built-in Interrupt Controller
— 31 Priority Levels, 256 Vectors
— 3.4 µs Latency @ 25 MHz
s Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
s 132-Lead Packages:
— Pin Grid Array (PGA)
— Plastic Quad Flat-Pack (PQFP)
The 80960KA is a member of Intel’s i960® 32-bit processor family, which is designed especially for embedded
applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960KA has a large
register set, multiple parallel execution units and a high-bandwidth burst bus. Using advanced RISC technology,
this high performance processor is capable of execution rates in excess of 9.4 million instructions per second*.
The 80960KA is well-suited for a wide range of applications including non-impact printers, I/O control and
specialty instrumentation.
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS
CONTROL
LOGIC
32-BIT
BURST
BUS
Figure 1. The 80960KA Processor’s Highly Parallel Architecture
* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
May 1993
© INTEL CORPORATION, 1993
Order Number: 270775-005



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80960KA
EMBEDDED 32-BIT MICROPROCESSOR
1.0 THE i960® PROCESSOR ................................ 1
1.1. Key Performance Features .......................... 2
1.1.1. Memory Space And Addressing Modes . 4
1.1.2. Data Types ............................................. 4
1.1.3. Large Register Set ................................. 4
1.1.4. Multiple Register Sets ............................ 5
1.1.5. Instruction Cache ................................... 5
1.1.6. Register Scoreboarding ......................... 5
1.1.7. High Bandwidth Local Bus ..................... 6
1.1.8. Interrupt Handling ................................... 6
1.1.9. Debug Features ..................................... 6
1.1.10. Fault Detection ..................................... 7
1.1.11. Built-in Testability ................................. 7
1.1.12. CHMOS ................................................ 7
2.0 ELECTRICAL SPECIFICATIONS .................. 10
2.1. Power and Grounding ................................ 10
2.2. Power Decoupling Recommendations ....... 10
2.3. Connection Recommendations .................. 11
2.4. Characteristic Curves ................................. 11
2.5. Test Load Circuit ........................................ 14
2.6. Absolute Maximum Ratings ....................... 15
2.7. DC Characteristics ..................................... 15
2.8. AC Specifications ....................................... 16
2.8.1. AC Specification Tables ....................... 17
3.0 MECHANICAL DATA ..................................... 21
3.1. Packaging .................................................. 21
3.1.1. Pin Assignment .................................... 21
3.2. Pinout ......................................................... 25
3.3. Package Thermal Specification ................. 29
4.0. WAVEFORMS ............................................... 33
5.0. REVISION HISTORY ..................................... 38
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
The 80960KA Processor’s Highly
Parallel Architecture ............................ i
80960KA Programming
Environment ........................................ 1
Instruction Formats ............................. 4
Multiple Register Sets Are Stored
On-Chip ............................................... 6
Connection Recommendations
for Low Current Drive Network .......... 11
Connection Recommendations
for High Current Drive Network ......... 11
Typical Supply Current vs.
Case Temperature ............................ 12
Typical Current vs. Frequency
(Room Temp) .................................... 12
Typical Current vs. Frequency
(Hot Temp) ........................................ 13
Worst-Case Voltage vs. Output
Current on Open-Drain Pins .............. 13
Capacitive Derating Curve ................ 13
Test Load Circuit for Three-State
Output Pins ...................................... 14
Test Load Circuit for Open-Drain
Output Pins ...................................... 14
Drive Levels and Timing Relationships
for 80960KA Signals ......................... 16
Processor Clock Pulse (CLK2) .......... 20
RESET Signal Timing ....................... 20
32-Lead Pin-Grid Array
(PGA) Package ................................. 21
80960KA PGA Pinout—View from
Bottom (Pins Facing Up) ................... 22
80960KA PGA Pinout—View from
Top (Pins Facing Down) .................... 23
80960KA 132-Lead Plastic Quad
Flat-Pack (PQFP) Package ............... 23
PQFP Pinout - View From Top .......... 24
HOLD Timing .................................... 30
16 MHz Maximum Allowable
Ambient Temperature ....................... 31
ii



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CONTENTS
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
20 MHz Maximum Allowable
Ambient Temperature ....................... 31
25 MHz Maximum Allowable
Ambient Temperature ....................... 32
Maximum Allowable Ambient
Temperature for the Extended
Temperature TA-80960KA at
20 MHz in PGA Package .................. 32
Non-Burst Read and Write
Transactions Without Wait States ..... 33
Burst Read and Write Transaction
Without Wait States ......................... 34
Burst Write Transaction with
2, 1, 1, 1 Wait States ........................ 35
Accesses Generated by Quad Word
Read Bus Request, Misaligned Two
Bytes from Quad Word Boundary
(1, 0, 0, 0 Wait States) ...................... 36
Interrupt Acknowledge Transaction .. 37
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
80960KA Instruction Set ..................... 3
Memory Addressing Modes ................ 4
80960KA Pin Description:
L-Bus Signals ...................................... 8
80960KA Pin Description:
Support Signals ................................... 9
DC Characteristics ............................ 15
80960KA AC Characteristics
(16 MHz) ........................................... 17
80960KA AC Characteristics
(20 MHz) ........................................... 18
80960KA AC Characteristics
(25 MHz) ........................................... 19
80960KA PGA Pinout —
In Pin Order ....................................... 25
80960KA PGA Pinout —
In Signal Order .................................. 26
80960KA PQFP Pinout —
In Pin Order ....................................... 27
80960KA PQFP Pinout —
In Signal Order .................................. 28
80960KA PGA Package
Thermal Characteristics .................... 29
80960KA PQFP Package
Thermal Characteristics .................... 30
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80960KA
1.0 THE i960® PROCESSOR
The 80960KA is a member of the 32-bit architecture
from Intel known as the i960 processor family. These
were especially designed to serve the needs of
embedded applications. The embedded market
includes applications as diverse as industrial
automation, avionics, image processing, graphics and
networking. These types of applications require high
integration, low power consumption, quick interrupt
response times and high performance. Since time to
market is critical, embedded microprocessors need to
be easy to use in both hardware and software
designs.
All members of the i960 processor family share a
common core architecture which utilizes RISC
technology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
Software written for the 80960KA will run without
modification on any other member of the 80960
Family. It is also pin-compatible with the 80960KB
which includes an integrated floating-point unit and
the 80960MC which is a military-grade version that
supports multitasking, memory management, multi-
processing and fault tolerance.
0000 0000H
ADDRESS SPACE
FETCH
INSTRUCTION CACHE
INSTRUCTION
STREAM
FFFF FFFFH
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
LOAD
STORE
INSTRUCTION
EXECUTION
PROCESSOR STATE
REGISTERS
INSTRUCTION
POINTER
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
SIXTEEN 32-BIT GLOBAL REGISTERS
g0
g15
REGISTER CACHE
SIXTEEN 32-BIT LOCAL REGISTERS
r0
r15
FOUR 80-BIT FLOATING POINT REGISTERS
CONTROL REGISTERS
Figure 2. 80960KA Programming Environment
1




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