80960HD Datasheet PDF - Intel Corporation


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80960HD
Intel Corporation

Part Number 80960HD
Description 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor
Page 30 Pages

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80960HA/HD/HT 32-Bit High-Performance
Superscalar Processor
Data Sheet
Advance Information
Product Features
s 32-Bit Parallel Architecture
—Load/Store Architecture
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers
—1.28 Gbyte Internal Bandwidth
(80 MHz)
—On-Chip Register Cache
s Processor Core Clock
—80960HA is 1x Bus Clock
—80960HD is 2x Bus Clock
—80960HT is 3x Bus Clock
s Binary Compatible with Other 80960
Processors
s Issue Up To 150 Million Instructions per
Second
s High-Performance On-Chip Storage
—16 Kbyte Four-Way Set-Associative
Instruction Cache
—8 Kbyte Four-Way Set-Associative Data
Cache
—2 Kbyte General Purpose RAM
—Separate 128-Bit Internal Paths For
Instructions/Data
s 3.3 V Supply Voltage
—5 V Tolerant Inputs
—TTL Compatible Outputs
s Guarded Memory Unit
—Provides Memory Protection
—User/Supervisor Read/Write/Execute
s 32-Bit Demultiplexed Burst Bus
—Per-Byte Parity Generation/Checking
—Address Pipelining Option
—Fully Programmable Wait State
Generator
—Supports 8-, 16- or 32-Bit Bus Widths
—160 Mbyte/s External Bandwidth
(40 MHz)
s High-Speed Interrupt Controller
—Up to 240 External Interrupts
—31 Fully Programmable Priorities
—Separate, Non-maskable Interrupt Pin
s Dual On-Chip 32-Bit Timers
—Auto Reload Capability and One-Shot
—CLKIN Prescaling, ÷1, 2, 4 or 8
—JTAG Support - IEEE 1149.1 Compliant
Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 272495-007
July, 1998



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80960HA/HD/HT
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 80960HA/HD/HT may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
Advance Information Datasheet



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80960HA/HD/HT
Contents
1.0 About This Document .............................................................................................. 1
2.0 Intel’s 80960Hx Processor...................................................................................... 1
2.1 The i960® Processor Family ................................................................................. 2
2.2 Key 80960Hx Features.......................................................................................... 2
2.2.1 Execution Architecture ............................................................................. 2
2.2.2 Pipelined, Burst Bus ................................................................................. 2
2.2.3 On-Chip Caches and Data RAM .............................................................. 3
2.2.4 Priority Interrupt Controller ....................................................................... 3
2.2.5 Guarded Memory Unit .............................................................................. 3
2.2.6 Dual Programmable Timers ..................................................................... 4
2.2.7 Processor Self Test .................................................................................. 4
2.3 Instruction Set Summary ....................................................................................... 5
3.0 Package Information................................................................................................. 6
3.1 Pin Descriptions .................................................................................................... 7
3.2 80960Hx Mechanical Data ..................................................................................12
3.2.1 80960Hx PGA Pinout .............................................................................12
3.2.2 80960Hx PQ4 Pinout..............................................................................18
3.3 Package Thermal Specifications .........................................................................23
3.4 Heat Sink Adhesives ...........................................................................................26
3.5 PowerQuad4 Plastic Package.............................................................................26
3.6 Stepping Register Information.............................................................................26
3.7 Sources for Accessories......................................................................................28
4.0 Electrical Specifications........................................................................................29
4.1 Absolute Maximum Ratings.................................................................................29
4.2 Operating Conditions...........................................................................................29
4.3 Recommended Connections ...............................................................................30
4.4 VCC5 Pin Requirements (VDIFF) .........................................................................30
4.5 VCCPLL Pin Requirements.................................................................................31
4.6 DC Specifications ................................................................................................32
4.7 AC Specifications ................................................................................................34
4.7.1 AC Test Conditions ................................................................................37
4.8 AC Timing Waveforms ........................................................................................38
5.0 Bus Waveforms.........................................................................................................46
5.1 80960Hx Boundary Scan Chain ..........................................................................76
5.2 Boundary Scan Description Language Example.................................................80
Advance Information Datasheet
iii



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80960HA/HD/HT
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80960Hx Block Diagram .......................................................................................1
80960Hx 168-Pin PGA Pinout — View from Top (Pins Facing Down) ...............12
80960Hx 168-Pin PGA Pinout — View from Bottom (Pins Facing Up) ...............13
80960Hx 208-Pin PQ4 Pinout .............................................................................18
Measuring 80960Hx PGA Case Temperature ....................................................23
80960Hx Device Identification Register ..............................................................26
VCC5 Current-Limiting Resistor ..........................................................................30
AC Test Load ......................................................................................................37
CLKIN Waveform ................................................................................................38
Output Delay Waveform......................................................................................38
Output Delay Waveform......................................................................................38
Output Float Waveform .......................................................................................39
Input Setup and Hold Waveform .........................................................................39
NMI, XINT7:0 Input Setup and Hold Waveform ..................................................39
Hold Acknowledge Timings .................................................................................40
Bus Backoff (BOFF) Timings ..............................................................................40
TCK Waveform....................................................................................................41
Input Setup and Hold Waveforms for TBSIS1 and TBSIH1 ....................................41
Output Delay and Output Float for TBSOV1 and TBSOF1 ......................................42
Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 ....................42
Input Setup and Hold Waveform for TBSIS2 and TBSIH2 ......................................42
Rise and Fall Time Derating at 85°C and Minimum VCC ....................................43
ICC Active (Power Supply) vs. Frequency ...........................................................43
ICC Active (Thermal) vs. Frequency ....................................................................44
Output Delay or Hold vs. Load Capacitance .......................................................44
Output Delay vs. Temperature ............................................................................45
Output Hold Times vs. Temperature ...................................................................45
Output Delay vs. VCC ..........................................................................................45
Cold Reset Waveform .........................................................................................46
Warm Reset Waveform .......................................................................................47
Entering ONCE Mode .........................................................................................48
Non-Burst, Non-Pipelined Requests without Wait States ...................................49
Non-Burst, Non-Pipelined Read Request with Wait States.................................50
Non-Burst, Non-Pipelined Write Request with Wait States .................................51
Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus .................52
Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus ......................53
Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus .................54
Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus ......................55
Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus ......................56
Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus ........................57
Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus .................58
Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus ......................59
Burst, Pipelined Read Request without Wait States, 32-Bit Bus.........................60
Burst, Pipelined Read Request with Wait States, 32-Bit Bus..............................61
Burst, Pipelined Read Request with Wait States, 8-Bit Bus................................62
Burst, Pipelined Read Request with Wait States, 16-Bit Bus..............................63
Using External READY........................................................................................64
Terminating a Burst with BTERM........................................................................65
BREQ and BSTALL Operation ............................................................................66
iv Advance Information Datasheet




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