The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
AD15-AD0 2-16, 39
I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and
data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-
D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory
or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-
dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-
ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”
or “grant sequence”.
O ADDRESS/STATUS: During T1, these are the four most signiﬁcant address lines for memory op-
erations. During I/O operations these lines are LOW. During memory and I/O operations, status
information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of
the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3
are encoded as shown.
This information indicates which segment register is presently being used for data accessing.
These lines are held at high impedance to the last valid logic level during local bus “hold ac-
knowledge” or “grant sequence”.
S4 S3 CHARACTERISTICS
0 0 Alternate Data
0 1 Stack
1 0 Code or None
1 1 Data
O BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to
enable data onto the most signiﬁcant half of the data bus, pins D15-D8. Eight bit oriented devices
tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE
is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-
ferred on the high portion of the bus. The S7 status information is available during T2, T3 and
T4. The signal is active LOW, and is held at high impedance to the last valid logic level during
interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during
T1 for the ﬁrst interrupt acknowledge cycle.
0 Whole Word
1 Upper Byte From/to Odd Address
0 Lower Byte From/to Even address
RD 32 O
READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-
pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on
the 80C86 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-
teed to remain HIGH in T2 until the 80C86 local bus has ﬂoated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-
READY: is the acknowledgment from the addressed memory or I/O device that will complete the
data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gener-
ator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.
Correct operation is not guaranteed if the Setup and Hold Times are not met.