74HCT574 Datasheet PDF - NXP


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74HCT574
NXP

Part Number 74HCT574
Description Octal D-type flip-flop
Page 18 Pages

74HCT574 datasheet pdf
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74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 7 — 4 March 2016
Product data sheet
1. General description
The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state
outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will
store the state of their individual D-inputs that meet the set-up and hold time requirements
on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume
a high-impedance OFF-state. Operation of the OE input does not affect the state of the
flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to
interface inputs to voltages in excess of VCC.
2. Features and benefits
Input levels:
For 74HC574: CMOS level
For 74HCT574: TTL level
3-state non-inverting outputs for bus oriented applications
8-bit positive, edge-triggered register
Common 3-state output enable input
Complies with JEDEC standard no. 7 A
Multiple package options
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74HC574D 40 C to +125 C SO20
74HCT574D
74HC574DB 40 C to +125 C SSOP20
74HCT574DB
74HC574PW 40 C to +125 C TSSOP20
74HCT574PW
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1



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NXP Semiconductors
4. Functional diagram
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Fig 1. Functional diagram
 '
 '
 '
 '
 '
 '
 '
 '
 &3
 2(
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WR
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4 
4 
4 
4 
4 
4 
4 
4 
PQD
' ' ' ' ' ' ' '
'4
&3
'4
&3
'4
&3
'4
&3
'4
&3
'4
&3
'4
&3
'4
&3
)) )) )) )) )) )) )) ))
&3
2(
4 4 4 4 4 4 4 4
DDK
Fig 2. Logic diagram
74HC_HCT574
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 18



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NXP Semiconductors
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state

&3
 '
4 
 '
4 
 '
4 
 '
4 
 '
4 
 '
4 
 '
4 
 '
4 
2(
 PQD
Fig 3. Logic symbol
5. Pinning information
5.1 Pinning
 &
 (1
 '















PQD
Fig 4. IEC logic symbol
+&
+&7
2( 
' 
' 
' 
' 
' 
' 
' 
' 
*1' 
Fig 5. Pin configuration SO20, SSOP20 and TSSOP20
 9&&
 4
 4
 4
 4
 4
 4
 4
 4
 &3
DDQ
5.2 Pin description
Table 2.
Symbol
OE
D[0:7]
GND
CP
Q[0:7]
VCC
Pin description
74HC_HCT574
Product data sheet
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
Description
3-state output enable input (active LOW)
data input
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
3-state flip-flop output
supply voltage
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 18



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NXP Semiconductors
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
Table 3. Function table[1]
Operating mode
Load and read register
Load register and disable output
Input
OE
L
L
H
H
CP
Dn
l
h
l
h
[1] H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition;
Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition.
7. Limiting values
Internal
flip-flop
L
H
L
H
Output
Qn
L
H
Z
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
SO20, SSOP20 and TSSOP20 packages
0.5
-
-
-
-
-
65
[1] -
+7
20
20
35
+70
70
+150
500
V
mA
mA
mA
mA
mA
C
mW
[1] For SO20: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
VCC
VI
VO
Tamb
supply voltage
input voltage
output voltage
ambient temperature
74HC574
Min Typ Max
2.0 5.0 6.0
0 - VCC
0 - VCC
40 +25 +125
74HCT574
Min Typ Max
4.5 5.0 5.5
0 - VCC
0 - VCC
40 +25 +125
Unit
V
V
V
C
74HC_HCT574
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 18




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