54ACT112 Datasheet PDF - National Semiconductor

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54ACT112
National Semiconductor

Part Number 54ACT112
Description Dual JK Negative Edge-Triggered Flip-Flop
Page 7 Pages


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September 1998
54ACT112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The ’ACT112 contains two independent, high-speed JK
flip-flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trigger-
ing occurs at a voltage level of the clock and is not directly
related to the transition time. The J and K inputs can change
when the clock is in either state without affecting the flip-flop,
provided that they are in the desired state during the recom-
mended setup and hold times relative to the falling edge of
the clock. A LOW signal on SD or CD prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW sig-
nals on SD and CD force both Q and Q HIGH.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
n ’ACT112 has TTL-compatible inputs
n Outputs source/sink 24 mA
n Standard Microcircuit Drawing (SMD) 5962-8995001
Connection Diagram
Pin Assigment for
DIP and Flatpack
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs
(Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
DS100976-3
Pin Assigment
for LCC
DS100976-5
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100976
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Logic Symbols
DS100976-1
IEEE/IEC
DS100976-2
DS100976-4
Truth Table
Inputs
Outputs
SD CD CP J K
L H X XX
Q
H
Q
L
H L X XX L H
L L X XX H H
H H M h h Q0 Q0
H H M lh L H
H H Mhl H L
H H M l l Q0 Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
M = HIGH-to-LOW Clock Transition
Q0 (Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock
transition.
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Logic Diagram (One Half Shown)
DS100976-6
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + O.5
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC +0.5V
±50 mA
±50 mA
−65˚C to +150˚C
Junction Temperature (TJ)
CDIP
175˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
4.5V to 5.5V
0V to VCC
0V to VCC
−55˚C to +125˚C
125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. Fairchild does not recom-
mend operation of FACTcircuits outside databook specifications.
DC Characteristics for ’ACT Family Devices
Symbol
VIH
VIL
VOH
Parameter
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
VCC TA = −55˚C to +125˚C
(V) Guaranteed Limits
4.5 2.0
5.5 2.0
4.5 0.8
5.5 0.8
4.5 4.4
5.5 5.4
4.5 3.70
5.5 4.70
VOL Maximum Low Level 4.5
Output Voltage
5.5
0.1
0.1
4.5 0.5
5.5 0.5
IIN
ICCT
IOLD
IOHD
ICC
Maximum Input Leakage
Current
Maximum ICC/Input
Minimum Dynamic
Output Current(Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
5.5
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
± 1.0
1.6
50
−50
80.0
Units
V
V
V
V
V
V
µA
mA
mA
mA
µA
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
IOUT = −50 µA
VIN = VIL or VIH
IOH = −24 mA
IOH = −24 mA
(Note 2)
IOUT = 50 µA
VIN = VIL or VIH
IOL = 24 MA
IOL = 24 mA
(Note 2)
VI = VCC, GND
VI = VCC − 2.1V
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC or GND
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