1 VIN System high potential input.
2 RSIG Signature resistor pin.
3 RCLASS Classification resistor pin.
4 AUX Auxiliary input power startup pin.
5 UVLO Line under-voltage lockout.
6 UVLORTN Return for the external UVLO resistors.
7 VEE System low potential input.
8 RTN System return for the PWM converter.
9 OUT Output of the PWM controller.
10 VCC Output of the internal high voltage
series pass regulator. Regulated output
voltage is nominally 7.8V.
11 FB Feedback signal.
12 COMP The output of the error amplifier and
input to the Pulse Width Modulator.
13 CS Current sense input.
14 RT / SYNC Oscillator timing resistor pin and
15 SS Soft-start input.
16 ARTN Analog PWM supply return.
The diode “OR” of several lines entering the PD, it is the more
positive input potential.
Connect a resistor from VIN to this pin for signature detection. The
resistor is in parallel with the UVLO resistors and should be valued
Connect the classification programming resistor from this pin to VEE.
A resistor divider between the AUX voltage input to VEE programs
the startup levels with a 2.5V threshold. A high value (>300kΩ)
internal pull down resistor is present to pull the pin low if it is left
open. In practice, the divider voltage should be set well above 2.5V
by the programming resistors.
An external resistor divider from VIN to UVLORTN programs the
shutdown levels with a 2.00V threshold at the UVLO pin. Hysteresis
is set by a switched internal 10uA current source that forces
additional current into the resistor divider.
Connect the bottom resistor of the resistor divider between the
UVLO pin and this pin.
Diode “OR’d” to the RJ45 connector and PSE’s –48V supply, it is
the more negative input potential.
The drain of the internal current limiting power MOSFET which
connects VEE to the return path of the dc-dc converter.
DC-DC converter gate driver output with 800mA peak sink current
When the auxiliary transformer winding (if used) raises the voltage
on this pin above the regulation set point, the internal series pass
regulator will shutdown, reducing the controller power dissipation.
Inverting input of the internal error amplifier. The non-inverting input
is internally connected to a 1.25V reference.
COMP pull-up is provided by an internal 5K resistor which may be
used to bias an opto-coupler transistor.
Current sense input for current mode control and over-current
protection. Current limiting is accomplished using a dedicated
current sense comparator. If the CS pin voltage exceeds 0.5V the
OUT pin switches low for cycle-by-cycle current limiting. CS is held
low for 50ns after OUT switches high to blank leading edge current
An external resistor connected from RT to ARTN sets the oscillator
frequency. This pin will also accept narrow ac-coupled
synchronization pulses from an external clock.
An external capacitor and an internal 10uA current source set the
soft-start ramp rate.
RTN for sensitive analog circuitry including the SMPS current limit