4069UB Datasheet PDF - ON Semiconductor

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4069UB
ON Semiconductor

Part Number 4069UB
Description Hex Inverter
Page 8 Pages


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MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs
Pin–for–Pin Replacement for CD4069UB
Meets JEDEC UB Specifications
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
Unit
V
V
mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
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PDIP–14
P SUFFIX
CASE 646
SOIC–14
D SUFFIX
CASE 751A
TSSOP–14
DT SUFFIX
CASE 948G
MARKING
DIAGRAMS
14
MC14069UBCP
AWLYYWW
1
14
14069U
AWLYWW
1
14
14
069U
ALYW
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC14069U
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14069UBCP PDIP–14
2000/Box
MC14069UBD
SOIC–14
2750/Box
MC14069UBDR2 SOIC–14 2500/Tape & Reel
MC14069UBDT TSSOP–14
96/Rail
MC14069UBDTEL TSSOP–14 2000/Tape & Reel
MC14069UBDTR2 TSSOP–14 2500/Tape & Reel
MC14069UBF SOEIAJ–14 See Note 1.
MC14069UBFEL SOEIAJ–14 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14069UB/D



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MC14069UB
PIN ASSIGNMENT
IN 1
OUT 1
IN 2
OUT 2
IN 3
OUT 3
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 6
12 OUT 6
11 IN 5
10 OUT 5
9 IN 4
8 OUT 4
LOGIC DIAGRAM
12
3
4
VDD = PIN 14
VSS = PIN 7
56
98
11 10
13 12
CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
VDD
INPUT*
OUTPUT
VSS
*Double diode protection on all
inputs not shown.
PULSE
GENERATOR
INPUT
VDD
14
OUTPUT
7 VSS
CL
20 ns
INPUT
tPHL
OUTPUT
90%
50%
10%
90%
50%
10%
tTHL
Figure 1. Switching Time Test Circuit and Waveforms
20 ns
VDD
VSS
tPLH
VOH
VOL
tTLH
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MC14069UB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic
Symbo VDD
– 55_C
25_C
125_C
l
Vdc Min
Max
Min
Typ (4.)
Max
Min
Max
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin= VDD
“0” Level VOL
5.0
0.05
10 — 0.05 —
15 — 0.05 —
0 0.05 — 0.05
0 0.05 — 0.05
0 0.05 — 0.05
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin = 0
“1” Level VOH 5.0 4.95 — 4.95
10 9.95 — 9.95
15 14.95 — 14.95
5.0
10
15
— 4.95 —
— 9.95 —
— 14.95 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 4.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 0.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
“0” Level VIL
5.0 —
10 —
15 —
1.0 —
2.0 —
2.5 —
2.25
4.50
6.75
“1” Level VIH
5.0 4.0 — 4.0 2.75
10 8.0 — 8.0 5.50
15 12.5 — 12.5 8.25
1.0 — 1.0
2.0 — 2.0
2.5 — 2.5
— 4.0 —
— 8.0 —
— 12.5 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 2.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 13.5 Vdc)
IOH
Source
5.0 – 3.0 — – 2.4 – 4.2
5.0 – 0.64 — – 0.51 – 0.88
10 – 1.6 — – 1.3 – 2.25
15 – 4.2 — – 3.4 – 8.8
— – 1.7 —
— – 0.36 —
— – 0.9 —
— – 2.4 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOL = 0.4 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink IOL
5.0 0.64
0.51
0.88
10 1.6 — 1.3 2.25
15 4.2 — 3.4
8.8
— 0.36 —
— 0.9 —
— 2.4 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current
Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Vin = 0)
Cin
5.0
7.5 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Per Package)
IDD 5.0 — 0.25 — 0.0005 0.25 —
10 — 0.5 — 0.0010 0.5 —
15 — 1.0 — 0.0015 1.0 —
7.5
15
30
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.)(6.)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Dynamic plus Quiescent,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPer Gate)(CL=50pF)
Output Rise and Fall Times (5.)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(CL = 50 pF)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH, tTHL = (1.35 ns/pF) CL+ 33 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH, tTHL = (0.60 ns/pF) CL+ 20 ns
tTLH, tTHL = (0.40 ns/pF) CL + 20 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagationDelayTimes (5.)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(CL = 50 pF)
tPLH, tPHL = (0.90 ns/pF) CL + 20 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH, tPHL = (0.36 ns/pF) CL + 22 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH, tPHL = (0.26 ns/pF) CL + 17 ns
IT
tTLH,
tTHL
5.0
10
15
5.0
10
15
tPLH,
tPHL
5.0
10
15
IT = (0.3 µA/kHz) f + IDD/6
IT = (0.6 µA/kHz) f + IDD/6
IT = (0.9 µA/kHz) f + IDD/6
— — 100 200 —
——
50 100 —
— — 40 80 —
——
——
——
65 125 —
40 75 —
30 55 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Unit
Vdc
Vdc
Vdc
Vdc
mAdc
mAdc
µAdc
pF
µAdc
µAdc
ns
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
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14
1
N
–T–
SEATING
PLANE
H
A
F
G
MC14069UB
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE M
8
B
7
C
K
D 14 PL
0.13 (0.005) M
J
L
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC
2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.290 0.310 7.37 7.87
M ––– 10_ ––– 10_
N 0.015 0.039 0.38 1.01
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