4066 Datasheet PDF - Fairchild Semiconductor

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4066
Fairchild Semiconductor

Part Number 4066
Description Quad Analog Switch
Page 9 Pages


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April 1994
Revised January 2000
74VHC4066
Quad Analog Switch
General Description
These devices are digitally controlled analog switches uti-
lizing advanced silicon-gate CMOS technology. These
switches have low “on” resistance and low “off” leakages.
They are bidirectional switches, thus any analog input may
be used as an output and visa-versa. Also the 4066
switches contain linearization circuitry which lowers the
“on” resistance and increases switch linearity. The 4066
devices allow control of up to 12V (peak) analog signals
with digital control signals of the same range. Each switch
has its own control input which disables each switch when
low. All analog inputs and outputs and digital inputs are
protected from electrostatic damage by diodes to VCC and
ground.
Features
s Typical switch enable time: 15 ns
s Wide analog input voltage range: 0–12V
s Low “on” resistance: 30 typ. ('4066)
s Low quiescent current: 80 µA maximum (74VHC)
s Matched switch characteristics
s Individual switch controls
s Pin and function compatible with the 74HC4066
Ordering Code:
Order Number Package Number
Package Description
74VHC4066M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74VHC4066MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC4066N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Schematic Diagram
Top View
Truth Table
Input
CTL
L
H
Switch
I/O–O/I
“OFF”
“ON”
© 2000 Fairchild Semiconductor Corporation DS011677
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC)
0.5 to +15V
DC Control Input Voltage (VIN)
1.5 to VCC + 1.5V
DC Switch I/O Voltage (VIO)
VEE 0.5 to VCC + 0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±25 mA
DC VCC or GND Current, per pin
(ICC)
±50 mA
Storage Temperature Range (TSTG)
65°C to +150°C
Power Dissipation (PD) (Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (TL)
(Soldering 10 seconds)
260°C
Min Max Units
Supply Voltage (VCC)
2 12 V
DC Input or Output Voltage
0 VCC V
(VIN, VOUT)
Operating Temperature Range (TA) 40 +85 °C
Input Rise or Fall Times (tr, tf)
VCC = 2.0V
1000 ns
VCC = 4.5V
500 ns
VCC = 9.0V
400 ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TA=25°C
TA=−40 to 85°C
Units
Typ Guaranteed Limits
VIH Minimum HIGH Level
Input Voltage
2.0V
4.5V
1.5
3.15
1.5
3.15
V
V
9.0V
6.3 5.3 V
12.0V
8.4 8.4 V
VIL Maximum LOW Level
Input Voltage
2.0V
4.5V
0.5
1.35
0.5
1.35
V
V
9.0V
2.7 2.7 V
12.0V
3.6 3.6 V
RON
Maximum “ON” Resistance
See (Note 5)
VCTL = VIH, IS = 2.0 mA
VIS = VCC to GND
(Figure 1)
4.5V
100
170
200
9.0V
50
85
105
12.0V
30
70
85
2.0V
120
180
215
VCTL = VIH, IS = 2.0 mA
VIS = VCC or GND
(Figure 1)
4.5V
9.0V
12.0V
50
35
20
80
60
40
100
75
60
RON
Maximum “ON” Resistance
Matching
VCTL = VIH
VIS = VCC to GND
4.5V
9.0V
12.0V
10
5
5
15
10
10
20
15
15
IIN Maximum Control
Input Current
IIZ Maximum Switch “OFF”
Leakage Current
IIZ Maximum Switch “ON”
Leakage Current
ICC Maximum Quiescent
Supply Current
VIN = VCC or GND
VCC = 2 6V
VOS = VCC or GND
VIS = GND or VCC
VCTL = VIL (Figure 2)
VIS = VCC to GND
VCTL = VIH
VOS = OPEN (Figure 3)
VIN = VCC or GND
IOUT = 0 µA
6.0V
9.0V
12.0V
6.0V
9.0V
12.0V
6.0V
9.0V
12.0V
10
15
20
10
15
20
±0.05
±60
±80
±100
±40
±50
±60
1.0
2.0
4.0
±0.5
±600
±800
±1000
±150
±200
±300
10
20
40
µA
nA
nA
nA
nA
nA
nA
µA
µA
µA
Note 4: For a power supply of 5V ± 10% the worst case on resistance (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 5: At supply voltages (VCC – GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
these devices be used to transmit digital only when using these supply voltages.
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AC Electrical Characteristics
VCC = 2.0V6.0V VEE = 0V12V, CL = 50 pF (unless otherwise specified)
Symbol
Parameter
Conditions
tPHL, tPLH Maximum Propagation
Delay Switch In to Out
tPZL, tPZH
Maximum Switch Turn
“ON” Delay
RL = 1 k
tPHZ, tPLZ
Maximum Switch Turn
“OFF” Delay
RL = 1 k
Minimum Frequency
Response (Figure 7)
20 log(VO/VI) = −3 dB
Crosstalk Between
any Two Switches
RL = 600
VIS = 2 VPP at (VCC/2)
(Note 6)(Note 7)
RL = 600, F = 1 MHz
(Note 7)(Note 8)
(Figure 8)
Peak Control to Switch
Feedthrough Noise
(Figure 9)
RL = 600, F = 1 MHz
CL = 50 pF
Switch OFF Signal
Feedthrough
Isolation
RL = 600, F = 1 MHz
V(CT) VIL
(Note 7)(Note 8)
(Figure 10)
THD
Total Harmonic
Distortion
RL = 10 k, CL = 50 pF,
F = 1 kHz
(Figure 11)
CIN Maximum Control
Input Capacitance
VIS = 4 VPP
VIS = 8 VPP
CIN Maximum Switch
Input Capacitance
CIN Maximum Feedthrough
Capacitance
VCTL = GND
CPD Power Dissipation
Capacitance
Note 6: Adjust 0 dBm for F = 1 kHz (Null RL/RON Attenuation).
Note 7: VIS is centered at VCC/2.
Note 8: Adjust input for 0 dBm.
VCC
3.3V
4.5V
9.0V
12.0V
3.3V
4.5V
9.0V
12.0V
3.3V
4.5V
9.0V
12.0V
4.5V
9.0V
4.5V
9.0V
4.5V
9.0V
4.5V
9.0V
4.5V
9.0V
TA=25°C
TA=−40 to 85°C
Typ Guaranteed Limits
25 30
20
5 10
13
48
10
37
11
30 58
73
12 20
25
6 12
15
5 10
13
60 100
125
25 36
45
20 32
40
15 30
38
40
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
52 dB
50 dB
100 mV
250 mV
42 dB
44 dB
.013 %
.008 %
5 10 10 pF
20 pF
0.5 pF
15 pF
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AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
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