4053 Datasheet PDF - Unisonic Technologies

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4053
Unisonic Technologies

Part Number 4053
Description Analog Multiplexer
Page 6 Pages


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UTC 4053
ANALOG MULTIPLEXERS/ DEMULTIPLEXERS
DESCRIPTION
The UTC 4053 are Triple SPDT analog multiplexers for
application as digitally–controlled analog switches.
FEATURES
* Analog Voltage Range (VDD – VEE) = 3.0 ~ 18 V
Note: VEE must beVSS
* Linearized Transfer Characteristics
* Pin–to–Pin Replacement for CD4053
CMOS IC
SOP-16
DIP-16
TSSOP-16
*Pb-free plating product number: 4053L
PIN CONFIGURATIONS
Y1 1
16 VDD
Y0 2
15 Y
Z1 3
14 X
Z4
Z0 5
UTC 4053
13 X1
12 X0
INH 6
11 A
VEE 7
10 B
VSS 8
9C
UTC UNISONIC TECHNOLOGIES CO., LTD.
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UTC 4053
UTC 4053 Triple 2–Channel Analog Multiplexer/Demultiplexer
CMOS IC
CONTROLS
SWITCHES
IN/OUT
6
11
10
9
12
13
2
1
5
3
INHIBIT
AX
B
C
X0 Y
X1
Y0
Y1
Z0 Z
Z1
14
15 COMMONS
OUT/IN
4
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must beVSS.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
DC Supply Voltage (Referenced to VEE, VSSVEE)
VDD
Input or Output Voltage (DC or Transient) (Referenced to VSS
for Control Inputs and VEE for Switch I/O)
Vin, Vout
Input Current (DC or Transient), per Control Pin
Iin
Switch Through Current
ISW
Power Dissipation. Per Package**
PD
Storage Temperature
Tstg
Lead Temperature (8 - Second Soldering)
TLead
* Maximum Ratings are those values beyond which damage to the device may occur.
** Temperature Derating: “DIP and SOP” Packages: – 7.0 mW/From 65~ 125
RATINGS
-0.5 ~ +18.0
-0.5 ~ VDD +0.5
±10
±25
500
-65 ~ +150
260
UNIT
V
V
mA
mA
mW
ELECTRICAL CHARACTERISTICS
(Ta=25, unless otherwise indicated.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP# MAX UNIT
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
Power Supply Voltage Range
VDD VDD – 3.0VSSVEE
3.0
18 V
Quiescent Current per Package
Control Inputs: Vin = VSS or VDD
Switch I/O: VEE VI/O VDD,
IDD
and Vswitch500mV*
VDD=5.0V
VDD=10V
VDD=15V
Ta=25only (The channel
0.005 5.0 µA
0.010
10
0.015
20
component, (Vin - Vout)/Ron, is
Total Supply Current (Dynamic Plus
Quiescent, Per Package)
ID(AV)
not included.)
VDD=5.0V
VDD=10V
VDD=15V
(0.07 µA/kHz) f + IDD Typical
(0.20 µA/kHz) f + IDD
(0.36 µA/kHz) f + IDD
µA
UTC UNISONIC TECHNOLOGIES CO., LTD.
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UTC 4053
CMOS IC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP# MAX UNIT
CONTROL INPUTS – INHIBIT A, B, C (Voltages Referenced to VSS)
Ron= per spec, Ioff = per spec
Low – Level Input Voltage
VIL
VDD=5.0V
VDD=10V
VDD=15V
Ron= per spec, Ioff = per spec
2.25
4.50
1.5
3.0
V
6.75
4.0
High – Level Input Voltage
Input Leakage Current
Input Capacitance
VIH
VDD=5.0V
VDD=10V
VDD=15V
Iin Vin= 0 or VDD, VDD=15V
Cin
3.5 2.75
7.0 5.50
11 8.25
±0.00001 ±0.1
5.0 7.5
V
µA
pF
SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to VEE)
Recommended Peak–to–Peak Voltage
Into or Out of the Switch
VI/O
Channel On or Off
0
VDD
VPP
Recommended Static or Dynamic
Voltage Across the Switch** (Figure 3)
Vswitch Channel On
0 600 mV
Output Offset Voltage
VOO Vin = 0V, No Load
Vswitch500mV*
10 µV
ON Resistance
ΔON Resistance Between Any Two
Channels in the Same Package
Off–Channel Leakage Current
(Figure 8)
Capacitance, Switch I/O
Capacitance, Common O/I
Capacitance, Feedthrough
(Channel Off)
Ron
Ron
Ioff
CI/O
CO/I
CI/O
Vin = VIL or VIH (Control), and
Vin = 0 to VDD (Switch)
VDD=5.0V
VDD=10V
VDD=15V
VDD=5.0V
VDD=10V
VDD=15V
Vin = VIL or VIH (Control)
Channel to Channel or Any
One Channel, VDD=15V
Inhibit = VDD
Inhibit = VDD
Pins Not Adjacent
Pins Adjacent
250
120
80
25
10
10
±0.05
10
17
0.15
0.47
1050
500
280
70
50
45
±100
nA
pF
pF
pF
#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential
performance.
* For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may
be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the
device will be unaffected unless the Maximum Ratings are exceeded. (See second page of this data sheet.)
UTC UNISONIC TECHNOLOGIES CO., LTD.
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UTC 4053
CMOS IC
ELECTRICAL CHARACTERISTICS*
(CL = 50pF, Ta=25, VEEVSS, unless otherwise indicated.)
PARAMETER
SYMBOL VDD – VEE Vdc
TEST CONDITIONS
MIN TYP# MAX UNIT
Propagation Delay Times
(Figure 4) Switch Input to
Switch Output (RL = 10 k)
tPLH, tPHL
Inhibit to Output
tPHZ, tPLZ
tPZH, tPZL
5.0 tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns
10 tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns
15 tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns
5.0 (RL=10k, VEE=VSS)Output “1” or “0”
10 to High Impedance, or High
15 Impedance to “1” or “0” Level
25 65
8.0 20 ns
6.0 15
275 550
140 280 ns
110 220
Control Input to Output
5.0
300 600
tPLH, tPHL
10 RL = 10 k, VEE = VSS
15
120 240 ns
80 160
Second Harmonic Distortion
10 RL = 10K, f = 1 kHz, Vin = 5 VPP
0.07
%
Bandwidth (Figure 5)
Off Channel Feedthrough
Attenuation (Figure 5)
BW
10
RL = 1k, Vin = 1/2 (VDD–VEE) p–p,
CL = 50pF, 20 Log (Vout/Vin) = -3dB)
10
RL = 1K, Vin = 1/2 (VDD – VEE) p–p
fin = 55 MHz
17
-50
MHz
dB
Channel Separation
(Figure 6)
10
RL = 1 k, Vin = 1/2 (VDD–VEE) p–p
fin = 3.0 MHz
-50
dB
Crosstalk, Control Input to
Common O/I (Figure 7)
10
R1 = 1 k, RL = 10 kControl
tTLH = tTHL = 20 ns, Inhibit = VSS)
* The formulas given are for the typical characteristics only at 25.
75 mV
# Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential
performance.
IN/OUT
VDD
VDD VDD
VEE
OUT/IN
LEVEL
CONVERTED
CONTROL
VDD
IN/OUT
OUT/IN
CONTROL
VEE
Figure 1. Switch Circuit Schematic
UTC UNISONIC TECHNOLOGIES CO., LTD.
www.unisonic.com.tw
4
QW-R502-036,A



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