4049B Datasheet PDF - NXP


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4049B
NXP

Part Number 4049B
Description HEX inverting buffers
Page 4 Pages

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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4049B
buffers
HEX inverting buffers
Product specification
File under Integrated Circuits, IC04
January 1995



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Philips Semiconductors
HEX inverting buffers
Product specification
HEF4049B
buffers
DESCRIPTION
The HEF4049B provides six inverting buffers with high
current output capability suitable for driving TTL or high
capacitive loads. Since input voltages in excess of the
buffers’ supply voltage are permitted, the buffers may also
be used to convert logic levels of up to 15 V to standard
TTL levels. Their guaranteed fan-out into common bipolar
logic elements is shown in the table below.
HEF4049BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4049BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4049BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
Guaranteed fan-out in common logic families
DRIVEN ELEMENT
standard TTL
74 LS
74 L
GUARANTEED
FAN-OUT
2
9
16
Fig.1 Functional diagram.
Fig.3 Logic diagram (one gate).
APPLICATION INFORMATION
Some examples of applications for the HEF4049B are:
LOCMOS to DTL/TTL converter
HIGH sink current for driving 2 TTL loads
HIGH-to-LOW level logic conversion
Input protection
Fig.2 Pinning diagram.
January 1995
Fig.4 Input protection circuit that allows input
voltages in excess of VDD.
FAMILY DATA, IDD LIMITS category BUFFERS
See Family Specifications
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Philips Semiconductors
HEX inverting buffers
Product specification
HEF4049B
buffers
DC CHARACTERISTICS
VSS = 0 V; VI = VSS or VDD
HEF
VDD
V
Output (sink)
current LOW
Output (source)
current HIGH
Output (source)
current HIGH
4,75
10
15
5
10
15
5
VO
V
SYMBOL
0,4
0,5
1,5
4,6
9,5
13,5
IOL
IOH
40
MIN. MAX.
3,5
12,0
24,0
0,52
1,3
3,6
Tamb (°C)
+25
MIN. MAX.
2,9
10,0
20,0
0,44
1,1
3,0
+85
MN. MAX.
2,3
8,0
16,0
0,36
0,9
2,4
mA
mA
mA
mA
mA
mA
2,5 IOH
1,7
1,4
1,1 mA
HEC
Output (sink)
current LOW
Output (source)
current HIGH
VDD
V
VO
V
SYMBOL
4,75
10
15
5
10
15
0,4
0,5
1,5
4,6
9,5
13,5
IOL
IOH
55
MIN. MAX.
3,6
12,5
25,0
0,52
1,3
3,6
Tamb (°C)
+25
MIN. MAX.
2,9
10,0
20,0
0,44
1,1
3,0
+125
MIN. MAX.
1,9
6,7
13,0
0,36
0,9
2,4
mA
mA
mA
mA
mA
mA
Propagation delays
In On
HIGH to LOW
LOW to HIGH
Output transition
times
HIGH to LOW
LOW to HIGH
VDD
V
SYMBOL TYP.
5 35
10 tPHL
15
15
12
5 50
10 tPLH
15
25
20
5 20
10 tTHL
15
10
7
5 60
10 tTLH
15
30
20
MAX.
70
30
25
100
50
40
40
20
14
120
60
40
TYPICAL EXTRAPOLATION
FORMULA
ns 26 ns + (0,18 ns/pF) CL
ns 11 ns + (0,08 ns/pF) CL
ns 9 ns + (0,05 ns/pF) CL
ns 23 ns + (0,55 ns/pF) CL
ns 14 ns + (0,23 ns/pF) CL
ns 12 ns + (0,16 ns/pF) CL
ns 3 ns + (0,35 ns/pF) CL
ns 3 ns + (0,14 ns/pF) CL
ns 2 ns + (0,09 ns/pF) CL
ns 10 ns + (1,0 ns/pF) CL
ns 9 ns + (0,42 ns/pF) CL
ns 6 ns + (0,28 ns/pF) CL
January 1995
3



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Philips Semiconductors
HEX inverting buffers
Product specification
HEF4049B
buffers
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
2 500 fi + ∑ (foCL) × VDD2
where
10
11 000 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
35 000 fi + ∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
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