4043B Datasheet PDF - NXP

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4043B
NXP

Part Number 4043B
Description Quadruple R/S latch with 3-state outputs
Page 5 Pages


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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4043B
MSI
Quadruple R/S latch with 3-state
outputs
Product specification
File under Integrated Circuits, IC04
January 1995



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Philips Semiconductors
Quadruple R/S latch with 3-state outputs
DESCRIPTION
The HEF4043B is a quadruple R/S latch with 3-state
outputs with a common output enable input (EO). Each
latch has an active HIGH set input (S0 to S3), an active
HIGH reset input (R0 to R3) and an active HIGH 3-state
output (O0 to O3).
When EO is HIGH, the state of the latch output (On) can be
determined from the function table below. When EO is
LOW, the latch outputs are in the high impedance
OFF-state. EO does not affect the state of the latch.
The high impedance off-state feature allows common
busing of the outputs.
Product specification
HEF4043B
MSI
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
HEF4043BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4043BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4043BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
PINNING
EO
S0 to S3
R0 to R3
O0 to O3
common output enable input
set inputs (active HIGH)
reset inputs (active HIGH)
3-state buffered latch outputs
FUNCTION TABLE
INPUTS
EO Sn
LX
HL
HH
HL
Rn
X
H
X
L
OUTPUT
On
Z
L
H
latched
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state immaterial
Z = high impedance state
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2



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Philips Semiconductors
Quadruple R/S latch with 3-state outputs
Product specification
HEF4043B
MSI
Fig.4 Logic diagram (one latch).
Fig.3 Logic diagram.
January 1995
3



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Philips Semiconductors
Quadruple R/S latch with 3-state outputs
Product specification
HEF4043B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL MIN.
TYP.
Propagation delays
Rn On
HIGH to LOW
Sn On
LOW to HIGH
Output transition
times
HIGH to LOW
LOW to HIGH
3-state propagation delays
Output disable times
EO On
HIGH
LOW
Output enable times
EO On
HIGH
LOW
Minimum Sn
pulse width; HIGH
Minimum Rn
pulse width; HIGH
5
10 tPHL
15
5
10 tPLH
15
5
10 tTHL
15
5
10 tTLH
15
5
10 tPHZ
15
5
10 tPLZ
15
5
10 tPZH
15
5
10 tPZL
15
5
10 tWSH
15
5
10 tWRH
15
30
20
16
30
20
16
90
35
25
65
25
15
60
30
20
60
30
20
45
20
10
50
20
10
25
15
10
40
20
15
15
10
8
15
10
8
MAX.
TYPICAL EXTRAPOLATION
FORMULA
180 ns
70 ns
50 ns
135 ns
50 ns
35 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
63 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
38 ns + (0,55 ns/pF) CL
14 ns + (0,23 ns/pF) CL
7 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
90 ns
35 ns
25 ns
100 ns
40 ns
25 ns
50 ns
30 ns
25 ns
80 ns
45 ns
35 ns
ns
ns
ns
ns
ns
ns
see also waveforms
Fig.5
January 1995
4



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