4042B Datasheet PDF - NXP

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4042B
NXP

Part Number 4042B
Description Quadruple D-latch
Page 6 Pages


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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4042B
MSI
Quadruple D-latch
Product specification
File under Integrated Circuits, IC04
January 1995



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Philips Semiconductors
Quadruple D-latch
Product specification
HEF4042B
MSI
DESCRIPTION
The HEF4042B is a 4-bit latch with four data inputs (D0 to
D3), four buffered latch outputs (O0 to O3), four buffered
complementary latch outputs (O0 to O3) and two common
enable inputs (E0 and E1). Information on D0 to D3 is
transferred to O0 to O3 while both E0 and E1 are in the
same state, either HIGH or LOW. O0 to O3 follow D0 to
D3 as long as both E0 and E1 remain in the same state.
When E0 and E1 are different, D0 to D3 do not affect O0 to
O3 and the information in the latch is stored.
O0 to O3 are always the complement of O0 to O3. The
exclusive-OR input structure allows the choice of either
polarity for E0 and E1. With one enable input HIGH, the
other enable input is active HIGH; with one enable input
LOW, the other enable input is active LOW.
Fig.2 Pinning diagram.
HEF4042BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4042BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4042BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
D0 to D3
E0 and E1
O0 to O3
O0 to O3
data inputs
enable inputs
parallel latch outputs
complementary parallel latch outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4042B are:
Buffer storage
Holding register
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
January 1995
2



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Philips Semiconductors
Quadruple D-latch
Product specification
HEF4042B
MSI
FUNCTION TABLE
E0 E1
LL
LH
HL
HH
OUTPUT On
Dn
latched
latched
Dn
Note
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage).
Fig.3 Logic diagram.
Fig.4 Logic diagram (one latch).
January 1995
3



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Philips Semiconductors
Quadruple D-latch
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL MIN. TYP. MAX.
Propagation delays
D O, O
HIGH to LOW
LOW to HIGH
E O, O
HIGH to LOW
LOW to HIGH
Output transition
times
HIGH to LOW
LOW to HIGH
Set-up time
DE
Hold time
DE
Minimum enable
pulse width
5
10 tPHL
15
5
10 tPLH
15
5
10 tPHL
15
5
10 tPLH
15
5
10 tTHL
15
5
10 tTLH
15
5
10 tsu
15
5
10 thold
15
5
10 tWE
15
95 190 ns
40 80 ns
30 55 ns
85 175 ns
40 75 ns
30 60 ns
130 260 ns
50 105 ns
35 75 ns
120 245 ns
50 105 ns
35 75 ns
60 120 ns
30 60 ns
20 40 ns
60 120 ns
30 60 ns
20 40 ns
30 10
ns
20 5
ns
20 5
ns
15 5
ns
15 0
ns
15 0
ns
90 45
ns
40 20
ns
30 15
ns
Product specification
HEF4042B
MSI
TYPICAL EXTRAPOLATION
FORMULA
67 ns + (0,55 ns/pF) CL
28 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
57 ns + (0,55 ns/pF) CL
28 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
102 ns + (0,55 ns/pF) CL
38 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
92 ns + (0,55 ns/pF) CL
38 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
see also waveforms
Figs 5 and 6
Dynamic power
dissipation per
package (P)
January 1995
VDD
V
TYPICAL FORMULA FOR P (W)
5 3800 fi + ∑ (foCL) × VDD2
10 15 700 fi + ∑ (foCL) × VDD2
15 41 100 fi + ∑ (foCL) × VDD2
4
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)



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