4030B Datasheet PDF - NXP


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4030B
NXP

Part Number 4030B
Description Quadruple exclusive-OR gate
Page 3 Pages

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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4030B
gates
Quadruple exclusive-OR gate
Product specification
File under Integrated Circuits, IC04
January 1995



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Philips Semiconductors
Quadruple exclusive-OR gate
DESCRIPTION
The HEF4030B provides the positive quadruple
exclusive-OR function. The outputs are fully buffered for
highest noise immunity and pattern insensitivity of output
impedance.
Product specification
HEF4030B
gates
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4030BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4030BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4030BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.2 Logic diagram (one gate).
TRUTH TABLE
I1 I2 O1
LLL
HLH
LHH
HH L
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2



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Philips Semiconductors
Quadruple exclusive-OR gate
Product specification
HEF4030B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL
TYP.
MAX.
Propagation delays
In On
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10 tPHL
15
5
10 tPLH
15
5
10 tTHL
15
5
10 tTLH
15
85 175
35 75
30 55
75 150
30 65
25 50
60 120
30 60
20 40
60 120
30 60
20 40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TYPICAL EXTRAPOLATION
FORMULA
57 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
47 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1 100 fi + ∑(fo CL) × VDD2
where
10
4 900 fi + ∑(fo CL) × VDD2
fi = input freq. (MHz)
15
14 400 fi + ∑(fo CL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3




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