40174BT Datasheet PDF - NXP

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40174BT
NXP

Part Number 40174BT
Description HFT40174BT
Page 5 Pages


40174BT datasheet pdf
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40174B
MSI
Hex D-type flip-flop
Product specification
File under Integrated Circuits, IC04
January 1995



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Philips Semiconductors
Hex D-type flip-flop
Product specification
HEF40174B
MSI
DESCRIPTION
The HEF40174B is a hex edge-triggered D-type flip-flop
with six data inputs (D0 to D5), a clock input (CP), an
overriding asynchronous master reset input (MR), and six
buffered outputs (O0 to O5). Information on D0 to D5 is
transferred to O0 to O5 on the LOW to HIGH transition of
CP if MR is HIGH. When LOW, MR resets all flip-flops
(O0 to O5 = LOW) independent of CP and D0 to D5.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF40174BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40174BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40174BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
PINNING
D0 to D5
CP
MR
O0 to O5
data inputs
clock input (LOW to HIGH; edge-triggered)
master reset input (active LOW)
buffered outputs
FUNCTION TABLE
INPUTS
CP D
H
MR
H
OUTPUT
O
H
LH
L
X H no change
XX L
L
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
2



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Fig.3 Logic diagram.



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Philips Semiconductors
Hex D-type flip-flop
Product specification
HEF40174B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL MIN. TYP. MAX.
Propagation delays
CP On
HIGH to LOW
LOW to HIGH
MR On
HIGH to LOW
Output transition times
HIGH to LOW
LOW to HIGH
Set-up time
Dn CP
Hold time
Dn CP
Minimum clock
pulse width; LOW
Minimum MR pulse
width; LOW
Recovery time
for MR
Maximum clock
pulse frequency
5
10 tPHL
15
5
10 tPLH
15
5
10 tPHL
15
5
10 tTHL
15
5
10 tTLH
15
5
10 tsu
15
5
10 thold
15
5
10 tWCPL
15
5
10 tWMRL
15
5
10 tRMR
15
5
10 fmax
15
75 155 ns
30 65 ns
20 45 ns
75 155 ns
30 65 ns
20 45 ns
85 175 ns
35 70 ns
25 50 ns
60 120 ns
30 60 ns
20 40 ns
60 120 ns
30 60 ns
20 40 ns
20 10
ns
10 5
ns
10 5
ns
10 0
ns
50
ns
50
ns
70 35
ns
30 15
ns
20 10
ns
70 35
ns
35 15
ns
25 10
ns
45 25
ns
20 10
ns
15 5
ns
5 11
MHz
15 30
MHz
20 45
MHz
TYPICAL EXTRAPOLATION
FORMULA
48 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
48 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
see also waveforms
Fig.4
January 1995
4



40174BT datasheet pdf
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NXP
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