4017 Datasheet PDF - Fairchild

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4017
Fairchild

Part Number 4017
Description Decade Counter/Divider
Page 7 Pages


4017 datasheet pdf
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October 1987
Revised January 2004
CD4017BC CD4022BC
Decade Counter/Divider with 10 Decoded Outputs
Divide-by-8 Counter/Divider with 8 Decoded Outputs
General Description
The CD4017BC is a 5-stage divide-by-10 Johnson counter
with 10 decoded outputs and a carry out bit.
The CD4022BC is a 4-stage divide-by-8 Johnson counter
with 8 decoded outputs and a carry-out bit.
These counters are cleared to their zero count by a logical
“1” on their reset line. These counters are advanced on the
positive edge of the clock signal when the clock enable sig-
nal is in the logical “0” state.
The configuration of the CD4017BC and CD4022BC per-
mits medium speed operation and assures a hazard free
counting sequence. The 10/8 decoded outputs are nor-
mally in the logical “0” state and go to the logical “1” state
only at their respective time slot. Each decoded output
remains high for 1 full clock cycle. The carry-out signal
completes a full cycle for every 10/8 clock input cycles and
is used as a ripple carry signal to any succeeding stages.
Features
s Wide supply voltage range: 3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power Fan out of 2 driving 74L
TTL compatibility: or 1 driving 74LS
s Medium speed operation: 5.0 MHz (typ.)
with 10V VDD
s Low power: 10 µW (typ.)
s Fully static operation
Applications
• Automotive
• Instrumentation
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering
Ordering Code:
Order Number Package Number
Package Description
CD4017BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4017BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4022BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4022BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Connection Diagrams
CD4017B
CD4022B
Top View
© 2004 Fairchild Semiconductor Corporation DS005950
Top View
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Logic Diagrams
CD4017B
Terminal No. 8 = GND
Terminal No. 16 = VDD
CD4022B
Terminal No. 16 = VDD
Terminal No. 8 = GND
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Absolute Maximum Ratings(Note 1)
(Note 2)
DC Supply Voltage (VDD)
Input Voltage (VIN)
Storage Temperature (TS)
Power Dissipation (PD)
Dual-In-Line
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
0.5 VDC to +18 VDC
0.5 VDC to VDD +0.5 VDC
65°C to +150°C
700 mW
500 mW
260°C
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (VDD)
Input Voltage (VIN)
Operating Temperature Range (TA)
+3 VDC to +15 VDC
0 to VDD VDC
55°C to +125°C
Note 1: Absolute Maximum Ratingsare those values beyond which the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be operated at these limits. The table of Recom-
mended Operating Conditionsand Electrical Characteristicsprovides
conditions for actual device operation.
Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 2)
Symbol
Parameter
Conditions
IDD Quiescent Device
VDD = 5V
Current
VDD = 10V
VDD = 15V
VOL LOW Level
|IO| < 1.0 µA
Output Voltage
VDD = 5V
VDD = 10V
VDD = 15V
VOH HIGH Level
|IO| < 1.0 µA
Output Voltage
VDD = 5V
VDD = 10V
VDD = 15V
VIL LOW Level
|IO| < 1.0 µA
Input Voltage
VDD = 5V, VO = 0.5V or 4.5V
VDD = 10V, VO = 1.0V or 9.0V
VDD = 15V, VO = 1.5V or 13.5V
VIH HIGH Level
|IO| < 1.0 µA
Input Voltage
VDD = 5V, VO = 0.5V or 4.5V
VDD = 10V, VO = 1.0V or 9.0V
VDD = 15V, VO = 1.5V or 13.5V
IOL LOW Level Output
VDD = 5V, VO = 0.4V
Current (Note 3)
VDD = 10V, VO = 0.5V
VDD = 15V, VO = 1.5V
IOH HIGH Level Output
VDD = 5V, VO = 4.6V
Current (Note 3)
VDD = 10V, VO = 9.5V
VDD = 15V, VO = 13.5V
IIN Input Current
VDD = 15V, VIN = 0V
VDD = 15V, VIN = 15V
Note 3: IOL and IOH are tested one output at a time.
55°C
+25°
+125°C
Units
Min Max Min Typ Max Min Max
5 0.3 5 150
10 0.5 10 300 µA
20 1.0 20 600
0.05
0.05
0.05
0 0.05
0 0.05
0 0.05
0.05
0.05
0.05
V
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
4.95
9.95
14.95
V
1.5 1.5 1.5
3.0 3.0 3.0 V
4.0 4.0 4.0
3.5
7.0
11.0
0.64
1.6
4.2
0.25
0.62
1.8
0.1
0.1
3.5 3.5
7.0 7.0
11.0 11.0
0.51 0.88
0.36
1.3 2.25
0.9
3.4 8.8
2.4
0.2 0.36
0.14
0.5 0.9
0.35
1.5
3.5
105
105
0.1
0.1
1.1
1.0
1.0
V
mA
mA
µA
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AC Electrical Characteristics (Note 4)
TA= 25°C, CL= 50 pF, RL= 200k, trCL and tfCL= 20 ns, unless otherwise specified
Symbol
Parameter
Conditions
CLOCK OPERATION
tPHL, tPLH Propagation Delay Time Carry Out Line
Carry Out Line
Decode Out Lines
tTLH, tTHL Transition Time Carry Out and Decode Out Lines
tTLH
tTHL
fCL Maximum Clock Frequency
tWL, tWH Minimum Clock Pulse Width
trCL, tfCL Clock Rise and Fall Time
tSU Minimum Clock Inhibit Data Setup Time
CIN Average Input Capacitance
Note 4: AC Parameters are guaranteed by DC correlated testing.
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
CL = 15 pF
Measured with
Respect to Carry
Output Line
Min
1.0
2.5
3.0
Typ
Max
Units
415 800
160 320
130 250
240 480
85 170
70 140
500 1000
200 400
160 320
ns
ns
ns
200 360
100 180
ns
80 130
100 200
50 100 ns
40 80
2
5 MHz
6
125 250
45 90 ns
35 70
20
15 µs
5
120 240
40 80 ns
32 65
5 7.5 pF
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, trCL and tfCL = 20 ns, unless otherwise specified
Symbol
Parameter
Conditions
RESET OPERATION
tPHL, tPLH
Propagation Delay Time
Carry Out Line
Carry Out Line
Decode Out Lines
tW
tREM
Minimum Reset
Pulse Width
Minimum Reset
Removal Time
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
CL = 15 pF
Min Typ
Max
Units
415 800
160 320
130 250
240 480
85 170
70 140
500 1000
200 400
160 320
200 400
70 140
55 110
75 150
30 60
25 50
ns
ns
ns
ns
ns
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